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T25S16AFEPR bảng dữ liệu(PDF) 40 Page - Shenzhen Huazhimei Semiconductor Co., Ltd |
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T25S16AFEPR bảng dữ liệu(HTML) 40 Page - Shenzhen Huazhimei Semiconductor Co., Ltd |
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40 / 74 page ![]() 40 Figure 7.2 Write Enable Instruction(SPI or QPI Mode) 7.1.3 Write Enable for Volatile Status Register (50h) The non-volatile Status Register bits described in section 6.2 can also be written to as volatile bits. This gives more flexibility to change the system configuration and memory protection schemes quickly without waiting for the typical non-volatile bit write cycles or affecting the endurance of the Status Register non-volatile bits. To write the volatile values into the Status Register bits, the Write Enable for Volatile Status Register (50h) instruction must be issued prior to a Write Status Register (01h) instruction. Write Enable for Volatile Status Register instruction (Figure 7.3) will not set the Write Enable Latch (WEL)bit, it is only valid for the Write Status Register instruction to change the volatile Status Register bit values. Figure 7.3 Write Enable for Volatile Status Register Instruction(SPI or QPI Mode) 7.1.4 Write Disable (04h) The Write Disable instruction (Figure 7.4) resets the Write Enable Latch (WEL) bit in the Status Register to a 0. The Write Disable instruction is entered by driving CS# low, shifting the instruction code “04h” into the DI pin and then driving CS# high. Note that the WEL bit is automatically reset after Power-up and upon completion of the Write Status Register, Page Program, Sector Erase, Block Erase and Chip Erase instructions. Figure 7.4 Write Disable Instruction(SPI or QPI Mode) 7.1.5 Write Status Register (01h/31h/11h) The Write Status Registers command allows the Status Registers to be written. Only non-volatile Status Register bits SRP0, SEC, TB, BP2, BP1, BP0 (SR1[7:2]) CMP, LB3, LB2, LB1, QE, SRP1 (SR2[6:0]), and HRSW, DRV1, DRV0, HFQ, WPS, LC[1:0] (SR3[7:4,2:0])can be written. All other Status Register bit locations are read-only and will not be affected by the Write Status Registers command. LB[3:0] are non-volatile OTP bits; once each is set to 1, it cannot be cleared to 0. The Status Register bits are shown in Section 6.2, Status Registers. Any reserved bits should only be written to their default value. To write non-volatile Status Register bits, a standard Write Enable (06h) command must previously have HM25Q128A |
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