DSP56857 datasheet(359/662 Pages) FREESCALE

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Clocks

Enhanced Synchronous Serial Interface (ESSI), Rev. 4

Freescale Semiconductor

12-59

•

0 = Data is not transferred from the Receive Shift Register (RXSR) to the Receive Data

(SRX) register, therefore the RDR and ROE flags are not set.

•

1 = The receive sequence proceeds normally. Data is received during slot N, and the RDR

flag is set.

During a disabled slot, no receiver full interrupt is generated. The DSC is interrupted only for

enabled slots.

When the bits in the RSM are changed, their settings affect the next frame reception. The frame

currently being received is not affected by the new RSM setting. If the RSM is read, it shows the

current setting. An ESSI reset (ESSIEN = 0) does not affect the contents of the TSM registers.

After a hardware RESET signal or executing a software RESET instruction, the RSM register is

reset to $FFFFFFFF; that value enables all 32-time slots for data reception. The receive DC

setting determines how many of these control bits are actually used.

12.9 Clocks

The ESSI uses the following three clocks, illustrated in Figure 12-33 and Figure 12-34:

•

Bit clock–Used to serially clock the data bits in and out of the ESSI port

•

Word clock–Used to count the number of data bits per word (8, 10, 12, or 16 bits)

•

Frame clock–Used to count the number of words in a frame

The bit clock is used to serially clock the data. The clock is visible on the SCK, for Asynchronous

transmit or Synchronous modes and SC0, for asynchronous receive clock operation pins. The

word clock is an internal clock used to determine when transmission of an 8, 10, 12, or 16 bit

word has completed. The word clock in turn then clocks the frame clock, which marks the

beginning of each frame. The frame clock can be viewed on the SC2 and SC1 pins. The bit clock

can be received from an ESSI clock pin or can be generated from the peripheral clock passed

through a divider, illustrated in Figure 12-35.

Figure 12-33. ESSI Clocking (8-Bit Words, 3 Time Slots / Frame)

TS0

TS1

TS2

TS0

TS1

TS2

Frame n

Frame n+1

Word_Clock

Data

(SCK, SC0)

(SC2, SC1)

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