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SPC564A80L7 bảng dữ liệu(PDF) 105 Page - STMicroelectronics

tên linh kiện SPC564A80L7
Giải thích chi tiết về linh kiện  Up to 4 multiply and accumulate operations per cycle
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SPC564A80L7 bảng dữ liệu(HTML) 105 Page - STMicroelectronics

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SPC564A74L7, SPC564A80B4, SPC564A80L7
Electrical characteristics
Doc ID 15399 Rev 9
105/157
CJITTER
CC
T
CLKOUT
period
jitter(6),(7),(8),(9)
Peak-to-peak (clock
edge to clock edge)
fSYS maximum
–5
5
% fCLKOUT
T
Long-term jitter
(avg. over 2 ms
interval)
–6
6
ns
tcst
CC
T
Crystal start-up time (10), (11)
——
10
ms
VIHEXT
CC
T
EXTAL input high voltage
Crystal
Mode(12)
Vxtal
+ 0.4
—
V
T
External
Reference(12),
(13)
VRC33
/2 +
0.4
VRC33
VILEXT
CC
T
EXTAL input low voltage
Crystal
Mode(12)
—
Vxtal -
0.4
V
T
External
Reference(12),
(13)
0
VRC33
/2 -
0.4
—
CC
T
XTAL load capacitance(10)
4MHz
5
30
pF
8MHz
5
26
12 MHz
5
23
16 MHz
5
19
20 MHz
5
16
40 MHz
5
8
tlpll
CC
P
PLL lock time (10), (14)
—
—
200
s
tdc
CC
T
Duty cycle of reference
—40
60
%
fLCK
CC
T
Frequency LOCK range
—
–6
6
% fsys
fUL
CC
T
Frequency un-LOCK range
—
–18
18
% fsys
fCS
fDS
CC
D
Modulation Depth
Center spread
±0.25
±4.0
%fsys
D
Down Spread
–0.5
–8.0
fMOD
CC
D
Modulation frequency(15)
—
—
100
kHz
1.
Considering operation with PLL not bypassed.
2.
All internal registers retain data at 0 Hz.
3.
“Loss of Reference Frequency” window is the reference frequency range outside of which the PLL is in self clocked mode.
4.
Self clocked mode frequency is the frequency that the PLL operates at when the reference frequency falls outside the fLOR
window.
Table 26.
PLLMRFM electrical specifications
(VDDPLL = 1.08 V to 3.6 V, VSS = VSSPLL = 0 V, TA = TL to TH) (continued)
Symbol
C
Parameter
Conditions
Value
Unit
min
max



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