SPC564A80L7 datasheet(29/157 Pages) STMICROELECTRONICS

29 / 157 page

SPC564A74L7, SPC564A80B4, SPC564A80L7

Introduction

Doc ID 15399 Rev 9

29/157

1.5.24

Power management controller (PMC)

The power management controller contains circuitry to generate the internal 3.3 V supply

and to control the regulation of 1.2 V supply with an external NPN ballast transistor. It also

contains low voltage inhibit (LVI) and power-on reset (POR) circuits for the 1.2 V supply, the

3.3 V supply, the 3.3 V/5 V supply of the closest I/O segment (VDDEH1) and the 5 V supply

of the regulators (VDDREG).

1.5.25

Nexus port controller

The NPC (Nexus Port Controller) block provides real-time Nexus Class3+ development

support capabilities for the SPC564A80 Power Architecture-based MCU in compliance with

the IEEE-ISTO 5001-2003 and 2010 standards. MDO port widths of 4 pins and 12 pins are

available in all packages.

1.5.26

JTAG

The JTAGC (JTAG Controller) block provides the means to test chip functionality and

connectivity while remaining transparent to system logic when not in test mode. Testing is

performed via a boundary scan technique, as defined in the IEEE 1149.1-2001 standard. All

data input to and output from the JTAGC block is communicated in serial format. The JTAGC

block is compliant with the IEEE 1149.1-2001 standard and supports the following features:

●

IEEE 1149.1-2001 Test Access Port (TAP) interface 4 pins (TDI, TMS, TCK, and TDO)

●

A 5-bit instruction register that supports the following IEEE 1149.1-2001 defined

instructions:

–

BYPASS, IDCODE, EXTEST, SAMPLE, SAMPLE/PRELOAD, HIGHZ, CLAMP

●

A 5-bit instruction register that supports the additional following public instructions:

–

ACCESS_AUX_TAP_NPC

–

ACCESS_AUX_TAP_ONCE

–

ACCESS_AUX_TAP_eTPU

–

ACCESS_CENSOR

●

3 test data registers to support JTAG Boundary Scan mode

–

Bypass register

–

Boundary scan register

–

Device identification register

●

A TAP controller state machine that controls the operation of the data registers,

instruction register and associated circuitry

●

Censorship Inhibit Register

–

64-bit Censorship password register

–

If the external tool writes a 64-bit password that matches the Serial Boot password

stored in the internal flash shadow row, Censorship is disabled until the next

system reset.

1.5.27

Development Trigger Semaphore (DTS)

SPC564A80 devices include a system development feature, the Development Trigger

Semaphore (DTS) module, that enables software to signal an external tool by driving a

persistent (affected only by reset or an external tool) signal on an external device pin. There

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