TNETV2501INPGF datasheet(163/197 Pages) TI1

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Electrical Specifications

163

December 2002 − Revised November 2008

SPRS206K

5.11 XF Timings

Table 5−21 assumes testing over recommended operating conditions (see Figure 5−25).

Table 5−21. XF Switching Characteristics

NO.

PARAMETER

MIN

MAX

UNIT

td(XF)

Delay time, CLKOUT high to XF high†

td(XF)

Delay time, CLKOUT high to XF low†

† In this case, CLKOUT refers to the CPU clock. Since CLKOUT cannot be programmed to reflect the CPU clock, there might be an extra delay

of a certain number of CPU clocks based on the ratio between the system clock shown on CLKOUT and the CPU clock. For example, if SYSCLK2

is shown on CLKOUT and SYSCLK2 is programmed to be half the CPU clock, there might be an extra delay of one CPU clock period between

the transition of CLKOUT and the specified timing. If system clock is programmed to be one-fourth of the CPU clock, there might be an extra delay

of 1, 2, or 3 CPU clocks between the transition of CLKOUT and the specified timing. The extra delay must be taken into account when considering

the MAX value for the timing under question. Note that if the CPU clock and the system clock shown on CLKOUT are operating at the same

frequency, there will be no extra delay in the specified timing.

CLKOUT

NOTE: The figure shows the case in which CLKOUT is programmed to show a system clock that is operating at the same frequency as

the CPU clock.

Figure 5−25. XF Timings

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