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Electrical Specifications
161
December 2002 − Revised November 2008
SPRS206K
R1
R4
R6
R3
R5
R7
RESET
EMIF Group†‡
High Group†§
Z Group†¶
R8
Input/Output Group†#
R9
Toggle Group†||
† The state of the DSP pins during power up is undefined until RESET is asserted. It is recommended that the RESET pin be kept low during
power up.
‡ EMIF group: EMIF.A[21:2], EMIF.ARE/SADS/SDCAS/SRE, EMIF.AOE/SOE/SDRAS, EMIF.AWE/SWE/SDWE, EMIF.ARDY, EMIF.CE0,
EMIF.CE1, EMIF.CE2, EMIF.CE3, EMIF.BE0, EMIF.BE1, EMIF.BE2, EMIF.BE3, EMIF.SDCKE, EMIF.SOE3, EMIF.HOLD, EMIF.HOLDA,
ECLKOUT1.
EMIF.ARDY and EMIF.HOLDA do not go to a high-impedance state during reset since they are input-only signals; they are included here simply
for completeness.
§ High group: IACK, XF, SCL (assumes external pullup on pin), SDA (assumes external pullup on pin), UART.TX, TDO.
¶ Z group: HRDY, HINT, DX1, DX0
# Input/Output group: PGPIO[45:0], HPI.HD[7:0], EMIF.D[31:0], HPI.HAS, HPI.HBIL, HCNTL1, HCNTL0, HCS, HR/W, HDS1, HDS2,
NMI/WDTOUT, GPIO[7:0], TIM0, TIM1, CLKR0, CLKX0, FSR0, FSX0, CLKR1, CLKX1, FSR1, FSX1, EMU0, EMU1/OFF. Signals in this group
switch to input mode with reset.
|| Toggle group: ECLKOUT2, CLKOUT. Pins in this group toggle with a default frequency during reset.
R2
Figure 5−22. Reset Timings



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