DSP56156ROM datasheet(24/76 Pages) MOTOROLA

24 / 76 page

AC Electrical Characteristics and Timing

DSP56156 Data Sheet

MOTOROLA

NOTES:

1. Circuit stabilization delay is required during reset when using an external clock in two cases:

• after power-on reset

• when recovering from Stop mode

2. When using fast interrupts, IRQA or IRQB is defined as level-sensitive, then timings 20 and 21

apply to prevent multiple interrupt service. To avoid these timing restrictions, the negative edge-trig-

gered mode is recommended when using fast interrupts.

3. The interrupt instruction fetch is visible on the pins only in Mode 3.

4. The minimum is specified for the duration of an edge triggered IRQA interrupt required to recover

from the Stop state. This is not the minimum required so that the IRQA interrupt is accepted.

5. Timing #22 is for all IRQx interrupts while timing #23 is only when exiting the Wait state.

6. Timing #22 triggers off T1 in the normal state and off phi1 when exiting the Wait state.

7. The instruction fetch is visible on the pins only in Mode 2 and Mode 3.

Figure 7 Asynchronous Reset Timing

Figure 8 Synchronous Reset Timing

RESET

D0-D15

A0-A15

PS/DS

R/W

First Fetch

VIHR

CLKO

RESET

A0-A15

PS/DS

R/W

Reset, Stop, Wait, Mode Select, and Interrupt Timing

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

DSP56156ROM bảng dữ liệu(PDF) 24 Page - Motorola, Inc