DSP56156ROM datasheet(72/76 Pages) MOTOROLA

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Design Considerations

MOTOROLA

DSP56156 Data Sheet

A four level board is recommended. The top layer (directly under the parts) and the bottom

layer should be interconnect layers. The two center layers should be power and ground.

Ground and power planes should be completely separated. The digital and analog power/

ground planes should not overlap. All codec pins should be over the analog planes. The ana-

log planes should not encompass any digital pins. All codec signal traces should be over the

analog planes.

Figure 47 shows that 0.1

µF bypass caps should be located as close to the pins being bypassed

as possible. The ground side of these caps should be connected as close as possible to the VCCA

pin. The ground side of the bypass cap should be connected to the VCCA pin by short traces.

Figure 47 Suggested Top Layer Bypassing

The pins with 0.1

µF bypass caps are VREF and GNDA. The largest size practical bypass

caps should also be added for each of these pins as well as for the VDIV pin; 10

µF bypass

caps should be considered a minimum value for the larger caps (65

µF on VDIV may be

used). These caps should be near the package but do not have to be right next to the pins.

The DAC outputs (SPKP and SPKM) should be run right next to each other as shown on Figure 48.

BIAS

AUX

MIC

0.1

µF

0.1

µF

Š10 µF

µF

10 k

Ω

Analog I/O Considerations

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

DSP56156ROM bảng dữ liệu(PDF) 72 Page - Motorola, Inc