DSP56156ROM datasheet(5/76 Pages) MOTOROLA

tên linh kiện	DSP56156ROM

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MOTOROLA

DSP56156 Data Sheet

Introduction

Pin Groupings

The DSP56156 is available in a 112-pin Ceramic Quad Flat Pack (CQFP) and a 112-pin Plastic

Thin Quad Flat Pack (TQFP). The input and output signals are organized into the functional

groups indicated in Table 3. Figure 2 illustrates the chip’s pin functions.

NOTE:

OVERBARS are used throughout this document to indicate a signal which is at Ground voltage (typi-

cally a TTL logic low — VIL or VOL) when the function is logically true. These signals are, likewise, at

VCC voltage (typically a TTL logic high — VIH or VOH) when the function is logically false.

Table 3 Functional Pin Groupings

Functional Group

Number of Pins

Address

Data Bus

Bus Control

Host Interface (HI)

Synchronous Serial Interfaces (SSI)

Timer Interface

Interrupt and Mode Control

Phase-Locked Loop (PLL) and Clock

On-Chip Emulation (OnCETM Port)

On-Chip Codec

Power (VCC)10

Ground (GND)

Total

112

Pin Groupings

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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