DS3134 datasheet(129/203 Pages) DALLAS

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DS3134

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8.2.2 Packet Descriptors

In main memory resides a contiguous section up to 65,536 quad dwords that make up the Transmit Packet

Descriptors. The Transmit Packet Descriptors are aligned on a quad dword basis and can be placed

anywhere in the 32-bit address space via the Transmit Descriptor Base Address (see Table 8.2.2A).

Associated with each descriptor is a data buffer. The data buffer can be up to 8191 bytes long and must

be a contiguous section of main memory. The host will inform the DMA of the actual size of the data

buffer via the Byte Count field that resides in the Packet Descriptor. If an outgoing packet requires more

space than the data buffer allows, then Packet Descriptors will be link-listed together by the Host to

provide a chain of data buffers. Figure 8.2.2A is an example of how three descriptors were linked

together for an incoming packet on HDLC Channel 7. Channel 3 only required a single data buffer and

hence only one Packet Descriptor was used. Figure 8.2.1A shows a similar example for channels5 and 1.

Packet Descriptors can be either pending (i.e. queued up by the host and ready for transmission by the

DMA) or completed (i.e. have been transmitted by the DMA and are available for processing by the host).

Pending Packet Descriptors are pointed to by the Pending Queue Descriptors and completed Packet

Descriptors are pointed to by the Done Queue Descriptors.

Transmit Descriptor Address Storage Table 8.2.2A

Acronym

Address

Transmit Descriptor Base Address 0 (lower word)

TDBA0

0850h

Transmit Descriptor Base Address 1 (upper word)

TDBA1

0854h

Transmit Descriptor Example Figure 8.2.2A

dmatde

CH 5 Single Sent Buffer Descriptor

Base + 00h

CH 7 1st Queued Buffer Descriptor

Base + 10h

Base + 20h

CH 7 Sent 1st Buffer Descriptor

Base + 30h

Free Descriptor

Base + 40h

Base + 50h

Free Descriptor

Base + 60h

Base + 70h

CH 7 Last Sent Buffer Descriptor

Base + 80h

Free Descriptor

Base + FFFD0h

Free Descriptor

Base + FFFF0h

CH 3 Single Queued Buffer Desc.

CH 7 2nd Queued Buffer Descriptor

CH 7 Last Queued Buffer Descriptor

Pending Queue Descriptor Address

Done Queue Descriptor Pointer

Maximum of 65536

Descriptors

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