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DS3134 bảng dữ liệu(PDF) 7 Page - Dallas Semiconductor |
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DS3134 bảng dữ liệu(HTML) 7 Page - Dallas Semiconductor |
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7 / 203 page ![]() DS3134 7 of 203 SECTION 1: INTRODUCTION The DS3134 Chateau device is a 256 channels HDLC controller. The primary features of the device are listed in Table 1A. This data sheet is split in Sections along the major the blocks of the device as shown in Figure 1A. Throughout the data sheet, certain terms will be used and these terms are defined in Table 1B. The DS3134 device is designed to meet certain specifications and a listing of these governing specifications is shown in Table 1C. DS3134 BLOCK DIAGRAM Figure 1A RC2 RD2 RS2 TC2 TD2 TS2 JTDO PCLK PAD[31:0] PRST* PCBE[3:0]* PPAR PFRAME* PIRDY* PTRDY* PSTOP* PIDSEL PDEVSEL* PREQ* PGNT* PPERR* PSERR* RC15 RD15 RS15 TC15 TD15 TS15 RC0 RD0 RS0 TC0 TD0 TS0 RC1 RD1 RS1 TC1 TD1 TS1 PXAS* PXDS* PXBLAST* JTRST* JTDI JTMS JTCLK LA[19:0] LD[15:0] LWR*(LR/W*) LRD*(LDS*) LIM LINT* LRDY* LMS LCS* LHOLD(LBR*) LHLDA(LBG*) LBGACK* blockdia LCLK Pin Names in ( ) are active when the device is in the MOT mode (i.e. LIM = 1) LBHE* JTAG Test Access (Sec. 11) Local Bus Block (Sec. 10) Layer One Block (Sec. 5) HDLC Block (Sec. 6) FIFO Block (Sec. 7) DMA Block (Sec. 8) PCI Block (Sec. 9) BERT (Sec. 5) Receive Direction Transmit Direction |
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