DS3134 datasheet(56/203 Pages) DALLAS

56 / 203 page

DS3134

56 of 203

5.2 PORT REGISTER DESCRIPTIONS

Receive Side Control Bits (one each for all 16 ports)

RP[n]CR where n = 0 to 15 for each Port

See the Register Map in Section 3

5432

RSS1

RSS0

RSD1

RSD0

VRST

RISE

RIDE

RICE

RCOFA

IERC

VLB

VTO

n/a

LLB

RUEN

RP[i]HS

Note: Bits that are underlined are read only, all other bits are read-write; default value for all bits is 0.

Bit 0 / Invert Clock Enable (RICE).

0 = do not invert clock (normal mode)

1 = invert clock (inverted clock mode)

Bit 1 / Invert Data Enable (RIDE).

0 = do not invert data (normal mode)

1 = invert data (inverted data mode)

Bit 2 / Invert Sync Enable (RISE).

0 = do not invert sync pulse (normal mode)

1 = invert sync pulse (inverted sync pulse mode)

Bit 3 / V.54 Detector Reset (VRST). Toggling this bit from a 0 to a 1 and then back to a 0 causes the

internal V.54 detector to be reset and begin searching for the V.54 loop up pattern. See Section 5.4 for

more details on the operation of the V.54 detector.

Bit 4 / Sync Delay Bit 0 (RSD0).

Bit 5 / Sync Delay Bit 1 (RSD1).

These two bits define the format of the sync signal that will be applied to the RS[n] input. These bits are

ignored if the port has been configured to operate in an unchannelized fashion (RUEN = 1).

00 = sync pulse is 0 clocks early

01 = sync pulse is 1/2 clock early

10 = sync pulse is 1 clock early

11 = sync pulse is 2 clocks early

DS3134 bảng dữ liệu(PDF) 56 Page - Dallas Semiconductor

DS3134 bảng dữ liệu(HTML) 56 Page - Dallas Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL