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DS3134 bảng dữ liệu(PDF) 85 Page - Dallas Semiconductor |
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DS3134 bảng dữ liệu(HTML) 85 Page - Dallas Semiconductor |
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85 / 203 page ![]() DS3134 85 of 203 Bit 6 / Transmit Corrupt FCS (TCFCS). When this bit is set low, the HDLC engine will allow the Frame Checksum Sequence (FCS) to be transmitted as generated. When this bit is set high, the HDLC engine will invert all the bits of the FCS before transmission occurs. This is useful in debugging and testing HDLC channels at the system level. 0 = generate FCS normally 1 = invert all FCS bits Bit 7 / Transmit Abort Enable (TABTE). When this bit is set low, the HDLC engine will perform normally only sending an Abort sequence (eight ones in a row) when an error occurs in the PCI Block or the FIFO underflows. When this bit is set high, the HDLC engine will continuously transmit an all ones pattern (i.e. an Abort sequence). This bit is still active when the HDLC engine is configured in the Transparent Mode (TTRANS = 1). Bits 8 to 11/ Transmit Flag Generation Bits 0 to 3 (TFG0/TFG1/TFG2/TFG3). These 4 bits determine how many flags and interfill bytes will be sent in between consecutive packets. TFG3 TFG2 TFG1 TFG0 Action 0 0 0 0 share closing and opening flag 0 0 0 1 closing flag / no interfill bytes / opening flag 0 0 1 0 closing flag / 1 interfill bytes / opening flag 0 0 1 1 closing flag / 2 interfill bytes / opening flag 0 1 0 0 closing flag / 3 interfill bytes / opening flag 0 1 0 1 closing flag / 4 interfill bytes / opening flag 0 1 1 0 closing flag / 5 interfill bytes / opening flag 0 1 1 1 closing flag / 6 interfill bytes / opening flag 1 0 0 0 closing flag / 7 interfill bytes / opening flag 1 0 0 1 closing flag / 8 interfill bytes / opening flag 1 0 1 0 closing flag / 9 interfill bytes / opening flag 1 0 1 1 closing flag / 10 interfill bytes / opening flag 1 1 0 0 closing flag / 11 interfill bytes / opening flag 1 1 0 1 closing flag / 12 interfill bytes / opening flag 1 1 1 0 closing flag / 13 interfill bytes / opening flag 1 1 1 1 closing flag / 14 interfill bytes / opening flag Bit 12 / Transmit Zero Stuffing Disable (TZSD). When this bit is set low, the HDLC engine will perform zero stuffing on the outgoing data stream. When this bit is set high, the outgoing data stream is not zero stuffed. This bit is ignored when the HDLC engine is configured in the Transparent Mode (TTRANS = 1). |
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