DS3134 datasheet(61/203 Pages) DALLAS

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DS3134

61 of 203

Port Mode

DS0 Channels

Available

Unchannelized Mode (RUEN/TUEN = 1)

Channelized T1 Mode (RUEN/TUEN = 0 & RSS0/TSS0 = 0 & RSS1/TSS1 = 0)

0 to 23

Channelized E1 Mode (RUEN/TUEN = 0 & RSS0/TSS0 = 1 & RSS1/TSS1 = 0)

0 to 31

Channelized 4.096 MHz Mode (RUEN/TUEN = 0 & RSS0/TSS0 = 0 &

RSS1/TSS1 = 1)

0 to 63

Channelized 8.192 MHz Mode (RUEN/TUEN = 0 & RSS0/TSS0 = 1 &

RSS1/TSS1 = 1)

0 to 127

Bit 8 / Channelized PORT RAM Select Bit 0 (CPRS0).

Bit 9 / Channelized PORT RAM Select Bit 1 (CPRS1).

00 = Channelized DS0 Data (C[n]DAT[j])

01 = Receive Configuration (R[n]CFG[j])

10 = Transmit Configuration (T[n]CFG[j])

11 = illegal selection

Bit 14 / Indirect Access Read/Write (IARW). When the host wishes to read data from the internal

Channelized PORT RAM, this bit should be written to a one by the host. This causes the device to begin

obtaining the data from the DS0 channel location indicated by the CHID bits and the PORT RAM

indicated by the CPRS0 and CPRS1 bits. During the read access, the IAB bit will be set to one. Once the

data is ready to be read from the CP[n]RD register, the IAB bit will be set to zero. When the host wishes

to write data to the internal Channelized PORT RAM, this bit should be written to a zero by the host.

This causes the device to take the data that is currently present in the CP[n]RD register and write it to the

PORT RAM indicated by the CPRS0 and CPRS1 bits and the DS0 channel indicated by the CHID bits.

When the device has completed the write, the IAB will be set to zero.

Bit 15 / Indirect Access Busy (IAB). When an indirect read or write access is in progress, this read only

bit will be set to a one. During a read operation, this bit will be set to a one until the data is ready to be

read. It will be set to zero when the data is ready to be read. During a write operation, this bit will be set

to a one while the write is taking place. It will be set to zero once the write operation has completed.

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