DS3134 datasheet(82/203 Pages) DALLAS

82 / 203 page

DS3134

82 of 203

Bit 2 & Bit 3 / Receive CRC Selection (RCRC0/RCRC1). These 2 bits are ignored if the HDLC

channel is set into Transparent mode (RTRANS = 1).

RCRC1

RCRC0

Action

no CRC verification performed

16-bit CRC (CCITT/ITU Q.921)

32-bit CRC

illegal state

Bit 4 / Receive Invert Data Enable (RID). When this bit is set low, the incoming HDLC packets are not

inverted before processing. When this bit is set high, the HDLC engine inverts all the data (flags,

information fields, and FCS) before processing the data. The data is not re-inverted before passing to the

FIFO.

0 = do not invert data

1 = invert all data (including flags and FCS)

Bit 5 / Receive Bit Flip (RBF). When this bit is set low, the HDLC engine will place the first HDLC bit

received in the lowest bit position of the PCI Bus bytes (i.e. PAD[0] / PAD[8] / PAD[16] / PAD[24]).

When this bit is set high, the HDLC engine will place the first HDLC bit received in the highest bit

position of the PCI Bus bytes (i.e. PAD[7] / PAD[15] / PAD[23] / PAD[31]).

0 = the first HDLC bit received is placed in the lowest bit position of the bytes on the PCI Bus

1 = the first HDLC bit received is placed in the highest bit position of the bytes on the PCI Bus

Bit 6 / Receive CRC Strip Enable (RCS). When this bit is set high, the FCS is not transferred through

to the PCI Bus. When this bit is set low, the HDLC engine will include the two byte FCS (16-bit) or four

byte FCS (32-bit) in the data that it transfers to the PCI Bus. This bit is ignored if the HDLC channel is

set into Transparent mode (RTRANS = 1).

0 = send FCS to the PCI Bus

1 = do not send the FCS to the PCI Bus

Bit 7 / Receive Abort Disable (RABTD). When this bit is set low, the HDLC engine will examine the

incoming data stream for the Abort sequence, which are seven or more consecutive ones. When this bit is

set high, the incoming data stream is not examined for the Abort sequence and if an incoming Abort

sequence is received, no action will be taken. This bit is ignored when the HDLC engine is configured in

the Transparent Mode (RTRANS = 1).

Bit 8 / Receive Zero Destuffing Disable (RZDD). When this bit is set low, the HDLC engine will zero

destuff the incoming data stream. When this bit is set high, the HDLC engine will not zero destuff the

incoming data stream. This bit is ignored when the HDLC engine is configured in the Transparent Mode

(RTRANS = 1).

DS3134 bảng dữ liệu(PDF) 82 Page - Dallas Semiconductor