CP3SP33SMSSLASHNOPB datasheet(292/407 Pages) TI1

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CP3SP33

SNOSCW5 – MAY 2013

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28.6 Freeze Mode

While Freeze mode is asserted, the module will exhibit the following behavior:

In master mode, the transaction will be stalled at the bit that which is being currently transferred. The

MSKn and MDOD- In signals will retain the current level. Once Freeze mode is de-asserted, the module

will complete the current transaction.

In slave mode, the module will continue to operate normally. Data will be shifted at the rate of the MSK

clock.

Reading the MWnDAT register will not cause the RBF flag to be cleared, and it will not update the read

buffer if new data is ready into the shift register.

28.7 Microwire Interface Registers

Software interacts with the Microwire interface by accessing the Microwire registers. There are three such

registers:

Table 28-2. Microwire Interface Registers

NAME

ADDRESS

DESCRIPTION

MW0CTL1

FF 8404h

Microwire Module 0 Control Register 1

MW1CTL1

FF 5804h

Microwire Module 1 Control Register 1

MW0CTL2

FF 840Ah

Microwire Module 0 Control Register 2

MW1CTL2

FF 580Ah

Microwire Module 1 Control Register 2

MW0STAT

FF 8408h

Microwire Module 0 Status Register

MW1STAT

FF 5808h

Microwire Module 1 Status Register

MW0DAT

FF 8400h

Microwire Module 0 Data Register

MW1DAT

FF 5800h

Microwire Module 1 Data Register

28.7.1 Microwire Module n Control Register 1 (MWnCTL1)

The MWnCTL1 registers are 16-bit, read/write registers used to control the Microwire module. To avoid

clock glitches, the MWEN bit must be clear while changing the states of any other bits in the register. At

reset, all non-reserved bits are cleared. The register format is shown below.

SCDV

SCIDL

SCM

EIW

EIR

EIO

ECHO

MOD

MNS

MWEN

MWEN The Microwire Enable bit controls whether the Microwire interface module is enabled.

0 – Microwire module disabled.

1 – Microwire module enabled.

Clearing this bit disables the module, clears the status bits in the Microwire status register (the

BSY, RBF, and OVR bits in MWnSTAT), and places the Microwire interface pins in the states

described below.

STATE WHEN DISABLED

MSKn

Master – SCIDL Bit

Slave – Input

MDIDOn

Master – Input

Slave – TRI-STATE

MDODIn

Master – Known value

Slave – Input

292

Dual Microwire/SPI Interfaces

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