CP3SP33SMSSLASHNOPB datasheet(294/407 Pages) TI1

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CP3SP33

SNOSCW5 – MAY 2013

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28.7.2 Microwire Module n Control Register 2 (MWnCTL2)

The MWnCTL2 registers are 16-bit, read/write registers used to enable DMA requests. At reset, all non-

reserved bits are cleared. The register format is shown below.

Reserved

EDW

EDR

The Enable DMA Read bit controls whether a DMA request is enabled when the RBF bit in the

MWnSTAT register is set.

0 – DMA request disabled.

1 – DMA request enabled.

EDW

The Enable DMA Read bit controls whether a DMA request is enabled when the BSY bit in the

MWnSTAT register is cleared.

0 – DMA request disabled.

1 – DMA request enabled.

28.7.3 Microwire Module n Status Register (MWnSTAT)

The MWnSTAT registers are 16-bit, read-only registers that shows the current status of the Microwire

interface module. At reset, all non-reserved bits are clear. The register format is shown below.

Reserved

OVR

RBF

BSY

The Busy bit, when set, indicates that the Microwire shift register is busy. In master mode, the

BSY bit is set when the MWnDAT register is written. In slave mode, the bit is set on the first

leading edge of MSKn when MWCSn is asserted or when the MWnDAT register is written,

whichever occurs first. In both master and slave modes, this bit is cleared when the Microwire

data transfer sequence is completed and the read buffer is ready to receive the new data; in

other words, when the previous data held in the read buffer has already been read. If the

previous data in the read buffer has not been read and new data has been received into the shift

contents of the shift register could not be transferred into the read buffer.

0 – Shift register is not busy.

1 – Shift register is busy.

RBF

The Read Buffer Full bit, when set, indicates that the read buffer is full and ready to be read by

software. It is set when the shift register loads the read buffer, which occurs upon completion of a

transfer sequence if the read buffer is empty. The RBF bit is updated when the MWnDAT register

is read. At that time, the RBF bit is cleared if the shift register does not contain any new data (in

other words, the shift register is not receiving data or has not yet received a full byte of data). The

RBF bit remains set if the shift register already holds new data at the time that MWnDAT is read.

In that case, MWnDAT is immediately reloaded with the new data and is ready to be read by

software.

0 – Read buffer is not full.

1 – Read buffer is full.

OVR

The Receive Overrun bit, when set in master mode, indicates that a receive overrun has

occurred. An overrun occurs when the read buffer is full, the 8-bit shift register is full, and a new

data transfer sequence starts. This bit is undefined in slave mode. The OVR bit, once set,

remains set until cleared by software. Software clears this bit by writing a 1 to its bit position.

Writing a 0 to this bit position has no effect. No other bits in the MWnSTAT register are affected

by writes to the register.

0 – No receive overrun has occurred.

1 – Receive overrun has occurred.

294

Dual Microwire/SPI Interfaces

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