CP3SP33SMSSLASHNOPB datasheet(290/407 Pages) TI1

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Bit 0

(LSB)

Bit 1

MSB - 2

MSB - 1

MSKn

End of Transfer

Sample

Point

Shift

Out

Data Out

MSB

Bit 0

(LSB)

Bit 1

MSB - 2

MSB - 1

Data In

MSB

DS351

CP3SP33

SNOSCW5 – MAY 2013

www.ti.com

Figure 28-6. Alternate Mode (SCIDL = 1)

28.3 Slave Mode

In slave mode, the MSKn pin is an input for the shift clock MSKn. MDIDOn is put in TRI-STATE mode

when MWCSn is inactive. Data transfer is enabled when MWCSn is active.

The slave starts driving MDIDOn when MWCSn is active. The most significant bit (lower byte in 8-bit mode

or upper byte in 16-bit mode) is output onto the MDIDOn pin first. After eight or sixteen clocks (depending

on the selected mode), the data transfer is completed.

If a new shift process starts before MWnDAT was written, i.e., while MWnDAT does not contain any valid

data, and the ECHO bit is set, the data received from MDODIn is transmitted on MDIDOn in addition to

being shifted to MWnDAT. If the ECHO bit is clear, the data transmitted on MDIDOn is the data held in the

MWnDAT register, regardless of its validity. The master may negate the MWCSn signal to synchronize the

bit count between the master and the slave. If the slave is the only slave in the system, MWCSn can be

tied to ground.

28.4 Interrupt Support

Interrupts may be enabled for any of the conditions shown in Table 28-1.

Table 28-1. Microwire Interrupt Trigger Condition

Interrupt Enable Bit

Status Bit in the

Condition

in the

Description

MWnSTAT Register

MWnCTRL1 Register

Not Busy

BSY

EIW

The shift register is ready for the next data transfer sequence.

Read Buffer Full

RBF

EIR

The read buffer is full and waiting to be unloaded.

Overrun

OVF

EIO

A new data transfer sequence started while both the shift register

and the read buffer were full.

290

Dual Microwire/SPI Interfaces

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