CP3SP33SMSSLASHNOPB datasheet(291/407 Pages) TI1

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MWSPI

Interrupt

OVR = 1

EIO

RBF = 1

EIR

BSY = 0

EIW

DS073

CP3SP33

www.ti.com

SNOSCW5 – MAY 2013

Figure 28-7 illustrates the interrupt generation logic of this module.

Figure 28-7. MWSPI Interrupts

Module 0 uses IRQ29, and module 1 uses IRQ10.

Because the interrupt request for module 1 can be handled by either the CPU or DSP interrupt controllers,

the interrupt request is passed through the Audio Subsystem Controller (ASC), which is programmed to

route it to the interrupt controller. To use the interrupt, it must be enabled at three levels:

•

Microwire module—the interrupt must be enabled in the MW1CTL1 register.

•

ASC module—the interrupt is assigned to ASC interrupt channel 0, so bit 0 in the ASCINTSEL register

must be clear to select the CPU interrupt controller or set to select the DSP interrupt controller.

•

Interrupt controller—the interrupt request must be enabled in the interrupt controller. For the CPU

interrupt controller, this is interrupt request IRQ10.

28.5 DMA Support

The Microwire module may be operated with either one or two DMA channels. Two DMA channels are

required for processor-independent full-duplex operation. Both receive and transmit DMA can be enabled

individually. If transmit DMA is enabled (EDW = 1), a DMA request is asserted every time the BSY flag is

cleared. Enabling receive DMA (EDR = 1) asserts a DMA request every time the Receive Buffer Full flag

(RBF) is set. The Enable Interrupt on Read (EIR) bit must be clear when the EDR bit is set to avoid an

interrupt request while using receive DMA. The Enable Interrupt on Write (EIW) bit must be clear when the

EDW bit is set. However, a data overrun condition may occur, so the Enable Interrupt on Overrun (EIO) bit

should be set.

Module 0 uses DMA requests 33 (read) and 34 (write), and module 1 uses DMA requests 18 (read) and

19 (write).

Because module 1 DMA requests can be handled by either the CPU or DSP DMA controllers, the DMA

requests are passed through the Audio Subsystem Controller (ASC), which is programmed to route them

to the DMA controller. To use the DMA requests, they must be enabled at three levels:

•

Microwire module—the DMA requests must be enabled using the EDR and EDW bits in the MW1CTL2

•

ASC module—the DMA requests are assigned to ASC DMA channels 18 (read) and 19 (write). These

channels are controlled by bits 2 and 3 in the ASCDMASEL1 register. The bits must be clear to select

the CPU DMA controller or set to select the DSP DMA controller. If the DSP DMA controller is

selected, the DSP DMA channel must be enabled in the ASCDDMASELn registers.

•

DMA controller—the DMA requests must be enabled in the DMA controller. For the CPU DMA

controller, these are DMA requests 18 (read) and 19 (write).

Dual Microwire/SPI Interfaces

291

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