CP3SP33SMSSLASHNOPB datasheet(288/407 Pages) TI1

288 / 407 page

CP3SP33

SNOSCW5 – MAY 2013

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28.1.2 Reading

The Microwire interface implements a double buffer on read. As illustrated in Figure 28-2, the double read

buffer consists of the 16-bit shift register and a read buffer.

The 16-bit shift register loads the read buffer with new data when the data transfer sequence is completed

and previous data in the read buffer has been read. In master mode, an overrun error occurs when the

read buffer is full, the 16-bit shift register is full and a new data transfer sequence starts.

When 8-bit mode is selected, the lower byte of the shift register is loaded into the lower byte of the read

buffer and the read buffer’s higher byte remains unchanged.

The RBF bit indicates if the MWnDAT register holds valid data. The OVR bit indicates that an overrun

condition has occurred.

28.1.3 Writing

The BSY bit indicates whether the MWnDAT register can be written. All write operations to the MWnDAT

results will occur if the MWnDAT register is written while the BSY bit is set.

28.1.4 Clocking Modes

Two clocking modes are supported:

•

Normal mode—output data transmitted on the MDODIn pin (master mode) or the MDIDOn pin (slave

mode) is clocked out on the falling edge of the shift clock MSKn. Input data, which is received via the

MDIDOn pin (master mode) or the MDODIn pin (slave mode), is sampled on the rising edge of MSKn.

•

Alternate mode—output data is shifted out on the rising edge of MSKn on the MDODIn pin (master

mode) or MDIDOn pin (slave mode). Input data, which is received via MDIDOn pin (master mode) or

MDODIn pin (slave mode), is sampled on the falling edge of MSKn.

The clocking mode is selected with the SCM bit. The SCIDL bit allows selection of the value of MSKn

when it is idle (when there is no data being transferred). In master mode, the MSKn clock frequency can

be programmed in the SCDV field of the MWnCTL1 register. Figure 28-3, Figure 28-4, Figure 28-5, and

Figure 28-6 show the data transfer timing for the normal and the alternate modes with the SCIDL bit clear

and set.

Note that when data is shifted out on MDODIn (master mode) or MDIDOn (slave mode) on the leading

edge of the MSKn clock, bit 15 (16-bit mode) is shifted out on the second leading edge of the MSKn clock.

When data are shifted out on MDODIn (master mode) or MDIDOn (slave mode) on the trailing edge of

MSKn, bit 15 (16-bit mode) is shifted out on the first trailing edge of MSKn.

28.2 Master Mode

In master mode, the MSKn pin is an output for the shift clock, MSKn. When data is written to the

MWnDAT register, eight or sixteen MSKn clocks, depending on the mode selected, are generated to shift

the 8 or 16 bits of data, and then MSKn goes idle again. The MSKn idle state can be either high or low,

depending on the SCIDL bit.

288

Dual Microwire/SPI Interfaces

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