CP3SP33SMSSLASHNOPB datasheet(293/407 Pages) TI1

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CP3SP33

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SNOSCW5 – MAY 2013

MNS

The Master/Slave Select bit controls whether the CP3SP33 is a master or slave. When clear,

the device operates as a slave. When set, the device operates as the master.

0 – CP3SP33 is slave.

1 – CP3SP33 is master.

MOD

The Mode Select bit controls whether 8- or 16-bit mode is used. When clear, the device

operates in 8-bit mode. When set, the device operates in 16-bit mode. This bit must only be

changed when the module is disabled or idle (MWnSTAT.BSY = 0).

0 – 8-bit mode.

1 – 16-bit mode.

ECHO The Echo Back bit controls whether the echo back function is enabled in slave mode. This bit

must be written only when the Microwire interface is idle (MWnSTAT.BSY=0). The ECHO bit is

ignored in master mode. The MWnDAT register is valid from the time the register has been

written until the end of the transfer. In the echo back mode, MDODIn is transmitted (echoed

back) on MDIDOn if the MWnDAT register does not contain any valid data. With the echo back

function disabled, the data held in the MWnDAT register is transmitted on MDIDOn, whether or

not the data is valid.

0 – Echo back disabled.

1 – Echo back enabled.

EIO

The Enable Interrupt on Overrun bit enables or disables the overrun interrupt. When set, an

interrupt is asserted when the Receive Overrun bit (MWnSTAT.OVR) is set. Otherwise, no

interrupt is asserted when an overrun occurs. This bit must only be enabled in master mode.

0 – Disable overrun interrupts.

1 – Enable overrun interrupts.

EIR

The Enable Interrupt for Read bit controls whether an interrupt is asserted when the read buffer

becomes full. When set, an interrupt is asserted when the Read Buffer Full bit (MWnSTAT.RBF)

is set. Otherwise, no interrupt is asserted when the read buffer is full.

0 – No read buffer full interrupt.

1 – Interrupt when read buffer becomes full.

EIW

The Enable Interrupt for Write bit controls whether an interrupt is asserted when the Busy bit

(MWnSTAT.BSY) is cleared, which indicates that a data transfer sequence has been completed

and the read buffer is ready to receive the new data. Otherwise, no interrupt is asserted when

the Busy bit is cleared.

0 – No interrupt on data transfer complete.

1 – Interrupt on data transfer complete.

SCM

The Shift Clock Mode bit selects between the normal clocking mode and the alternate clocking

mode. In the normal mode, the output data is clocked out on the falling edge of MSKn and the

input data is sampled on the rising edge of MSKn. In the alternate mode, the output data is

clocked out on the rising edge of MSKn and the input data is sampled on the falling edge of

MSKn.

0 – Normal clocking mode.

1 – Alternate clocking mode.

SCIDL The Shift Clock Idle bit controls the value of the MSKn output when the Microwire module is idle.

This bit must be changed only when the Microwire module is disabled (MEN = 0) or when no

bus transaction is in progress (MWnSTAT.BSY = 0).

0 – MSKn is low when idle.

1 – MSKn is high when idle

SCDV

The Shift Clock Divider Value field specifies the divisor used for generating the MSKn shift clock

from the PCLK Clock. The divisor is 2 × (SCDV6:0 + 1). Valid values are 0000001b to

1111111b, so the division ratio may range from 4 to 256. This field is ignored in slave mode

(MWnCTL1.MNS = 0).

Dual Microwire/SPI Interfaces

293

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