CP3SP33SMSSLASHNOPB datasheet(296/407 Pages) TI1

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Start

Condition

Stop

Condition

SDA

SCL

DS076

SDA

Data Line

Stable:

Data Valid

Change

of Data

Allowed

SCL

DS075

CP3SP33

SNOSCW5 – MAY 2013

www.ti.com

During data transactions, the master device initiates the transaction, generates the clock signal, and

terminates the transaction. For example, when the ACB initiates a data transaction with an ACCESS.bus

peripheral, the ACB becomes the master. When the peripheral responds and transmits data to the ACB,

their master/slave (data transaction initiator and clock generator) relationship is unchanged, even though

their transmitter/receiver functions are reversed.

29.1.1 Data Transactions

One data bit is transferred during each clock period. Data is sampled during the high phase of the serial

clock

(SCL).

Consequently,

throughout

the

clock

high

phase,

the

data

must

remain

stable

(see Figure 29-1). Any change on the SDA signal during the high phase of the SCL clock and in the

middle of a transaction aborts the current transaction. New data must be driven during the low phase of

the SCL clock. This protocol permits a single data line to transfer both command/control information and

data using the synchronous serial clock.

Figure 29-1. Bit Transfer

Each data transaction is composed of a Start Condition, a number of byte transfers (programmed by

software), and a Stop Condition to terminate the transaction. Each byte is transferred with the most

significant bit first, and after each byte, an Acknowledge signal must follow.

At each clock cycle, the slave can stall the master while it handles the previous data, or prepares new

data. This can be performed for each bit transferred or on a byte boundary by the slave holding SCL low

to extend the clock-low period. Typically, slaves extend the first clock cycle of a transfer if a byte read has

not yet been stored, or if the next byte to be transmitted is not yet ready. Some microcontrollers with

limited hardware support for ACCESS.bus extend the access after each bit, to allow software time to

handle this bit.

29.1.1.1 Start and Stop

The ACCESS.bus master generates Start and Stop Conditions (control codes). After a Start Condition is

generated, the bus is considered busy and it retains this status until a certain time after a Stop Condition

is generated. A high-to-low transition of the data line (SDA) while the clock (SCL) is high indicates a Start

Condition. A low-to-high transition of the SDA line while the SCL is high indicates a Stop Condition (see

Figure 29-2).

Figure 29-2. Start and Stop Conditions

296

Dual ACCESS.bus Interfaces

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