VX6854LC datasheet(26/114 Pages) STMICROELECTRONICS

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Functional description

VX6854LC

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DocID027110 Rev 2

3.4.4

Failsafe signals

All signals going into the VX6854LC must be either at a low state or high impedance when

power is removed from the device. The exceptions to this rule are the EXTCLK,

XSHUTDOWN and the CCI signals. These pads have been designed to be high impedance

when the VX6854LC is powered-down. This means that the input signal on the specified

pads can either be high or low with no leakage problems.

3.5

Clock and frame rate timing

3.5.1

Video frame rate control

The output frame rate of VX6854LC can be reduced by extending either the line length or

the frame length. The extension is achieved by adding extra blanking bytes at the end of a

line or “blank” video lines to act as timing padding. The frame rate can be reduced from the

default 20 frame/s at 3.15 Mpixel resolution to less than 3 frame/s at 3.15 Mpixel resolution.

The advantage of the frame extension approach is that it does not reduce the pixel readout

rate or the active frame time and therefore does not introduce unwanted motion distribution

effects to the image.

3.5.2

PLL and clock input

The VX6854LC has an embedded PLL block. This block generates all necessary internal

clocks from an input range defined in Table 11. The input clock pad accepts sine wave or

square wave.

Table 11. System input clock frequency range

Minimum (MHz)

Maximum (MHz)

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