VX6854LC datasheet(17/114 Pages) STMICROELECTRONICS

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VX6854LC

Functional description

This chapter details the main blocks in the device in the following sections:

•

Section 3.1: Analog video block

•

Section 3.2: Digital video block

•

Section 3.4: Power management on page 19

This chapter also describes:

•

the device’s operating modes, see Section 3.3 on page 18

•

clock and frame rate control, see Section 3.5 on page 26

•

control and video interface formats, see Section 3.6 on page 28

3.1

Analog video block

The analog video block, shown in Figure 5, consists of a 3.15 Mpixel resolution pixel array,

power management circuitry. The digital block provides all timing signals to drive the analog

block.

Figure 5. Overview of analog video block

Pixel voltage values are read out and digitized using the address decoders and column

ADC.

3.15MP

pixel array

Y address

Digital

logic

raw sensor data

Timing signals

Power

management

SRAM readout

X-Address

Column ADC

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