VX6854LC datasheet(20/114 Pages) STMICROELECTRONICS

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Functional description

VX6854LC

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DocID027110 Rev 2

3.4.1

Power-up procedure

The digital and analog supply voltages can be powered up in any order for example, VDIG

then VANA or VANA then VDIG. See Table 8 for timing constraints.

On power-up the on-chip power-on reset cell ensures that the CCI register values are

initialized correctly to their default values.

The EXTCLK clock can either be initially low and then enabled during software standby

mode or EXTCLK can be a free running clock.

Table 8. Power-up sequence timing constraints for CCP2/CSI2 communications

Symbol

Parameter

Min.

Max.

Units

VANA rising – VDIG rising

VANA and VDIG may rise in any

order

The rising separation can vary from

0 ns to indefinite

VDIG rising – VANA rising

VANA/VDIG – XSHUTDOWN

rising

XSHUTDOWN must rise coincident

with, or later than, both power

supplies (VDIG and VANA)

XSHUTDOWN – first I2C

transaction with free running

clock

5(1)

5 ms is necessary to upload the NVM data into firmware registers and get the FW ready for sensor

initialization through I2C writes.

-ms

Minimum period with EXTCLK

present prior to the first I2C

transaction. Gated clock.

5(2)

For gated clock.

-ms

PLL start up/lock time

Entering streaming mode – first

frame start sequence (fixed part)

-10

Entering streaming mode – first

frame start sequence (variable

part) = Integration time

fine_integration_

time_min

-ms

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