VX6854LC datasheet(62/114 Pages) STMICROELECTRONICS

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Video timing

VX6854LC

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DocID027110 Rev 2

The equation relating the input clock frequency to pixel clock frequencies are given below:

6.2.2

Spread spectrum clock generator

The PLL contains a spread spectrum clock generator block (SSCG) for the purposes of EMI

reduction. This feature is off by default and is intended for use if channel blocking becomes

an issue on the baseband platform. A primary source of EMI is the high speed CCP serial

data link. The modulation period and depth are fully programmable. The spread mode is

selectable between center spread (default) or down spread. The SSCG registers can only

be reprogrammed with new values when the sensor is in software standby mode.

6.2.3

Framerate

The framerate of the array readout and therefore the output framerate is governed by the

line length, frame length and the video timing pixel clock frequency.

•

Line length is specified as a number of pixel clocks, line_length_pck.

•

Frame length is specified as a number of lines, frame_length_lines.

•

Video timing pixel clock is specified in MHz, vt_pix_clk_freq_mhz.

The equation relating the framerate to the Line length, frame length and the video timing

pixel clock frequency is given below:

Table 45 provides examples of frame timing for Raw10 mode for 20 fps for a variety of

external clock frequencies.

Table 46 provides examples of frame timing for Raw10 mode for 15 fps for a variety of

external clock frequencies.

vt_pix_clk_freq_mhz

ext_clk_freq_mhz

pll_multiplier

pre_pll_clk_div

vt_sys_clk_div

vt_pix_clk_div

--------------------------------------------------------------------------------------------------------------------------------

op_pix_clk_freq_mhz

ext_clk_freq_mhz

pll_multiplier

pre_pll_clk_div

op_sys_clk_div

op_pix_clk_div

-------------------------------------------------------------------------------------------------------------------------------------

Table 45. External clock frequency examples, 3.15 Mpixel Raw10 20 fps (CSI-2 only)

Ext Clk

Freq

Pre-PLL

Clk Div

PLL

multiplier

VT Sys

Clk Div

VT pixel

Clk Div

Video

timing

pixel

clock

Line length

Frame

length

MHz

Integer

(Dec)

Integer

MHz

Pixel

Clks

µs

Lines

(Dec)

9.60

79.680

2500

31.37

1594

12.00

133

79.800

2500

31.32

1596

13.00

123

79.950

2500

31.27

1599

Framerate

vt_pix_clk_freq_mhz

line_length_pck

frame_length_lines

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