VX6854LC datasheet(64/114 Pages) STMICROELECTRONICS

64 / 114 page

Video timing

VX6854LC

64/114

DocID027110 Rev 2

Derating shows the difference between the video timing domain and the output clock

domain.

FIFO

The FIFO is used to implement the data rate reduction required for profile 1 and 2 operation.

The concept of an output frame length and a line length for the output timing domain does

not exist for SMIA devices such as the VX6854LC. This is a result of the FIFO input data

patterns being different depending on scaling factor and if the data is co-sited or bayer

sampled, which results in variable interframe and interline blanking time between lines and

between frames.

Figure 23. SMIA output timing

When the FIFO reaches a certain level of usage the CCP transmitter starts outputting a line

containing x_output_size pixels. This then naturally tracks any variation in the input data

rate, if the water mark is set correctly underflow is not possible.

Figure 24. FIFO water mark control

If the derating factor >= downscale factor then the average input rate of a burst of a line of

scaler output data into the FIFO is always faster than the output data rate, in this case the

derating =

vt_sys_clk_div *

op_pix_clk_div

op_sys_clk_div *

vt_pix_clk_div

output data:

CCP Active video

2064 pixels

1552 lines

Line Blanking

Output line length

Does Not exist in SMIA

FIFO Water Mark Level = CCP Output Trigger

FIFO

Usage

LE CS

DATA

x_output_size + additional_cols

VX6854LC bảng dữ liệu(PDF) 64 Page - STMicroelectronics