L9662 datasheet(39/80 Pages) STMICROELECTRONICS

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L9662

Functional description

3.4.5

SPI register definition for squib functions

The SPI provides access to read/write to the registers internal to the device. All commands

and responses sent to/from the ASIC on SPI1 shall use set D13 as required for odd parity

on the 16 bit word. The responses to the commands are sent in the next valid CS_D.

The table below summarizes the MISO register mode response of various events and MOSI

messages. After POR event, RESETB negated, and loss of GND, the device sends 0x0000

in MISO for the first SPI transmission.

The MISO response shown here is the one received in the next valid SPI transmission after

each event or MOSI write.

Note:

X in software reset response should be interpreted as follows: D11=1;D10=0;D9:D8=CL bits

The SPI fault responses (0xD000 or 0xD003) indicate a fault in the last MOSI transmission.

The device uses the parity bit to determine the integrity of the MOSI command transmission.

Squib SPI commands

The following modes are supported by the squib ASIC using SPI1.



Configuration mode



Deployment mode



Diagnostic mode



Monitor mode

The table below is a summary of the modes and the functions that are achieved by sending

the particular MOSI command. The following sections will provide a full description of bit

settings for each mode. All commands and responses use D13 to achieve odd parity.

Table 15. MISO responses to various events

Event/MOSI message

MISO response

MOSI Parity error or message error during a deployment

0xD000

MOSI transmission - Incorrect number of clocks/bits

0xD003

Incorrect firing sequence received (Firing Command without

a valid Arm Command)

0xD005

Error due to message not allowed during deployment

0xD009

POR

0x0000

RESETB

0x0000

LOSS OF GND

0x0000

RIREF out of range

0x0000

MOSI Write Soft Reset: $AA

0x1X02

MOSI Write Soft Reset: $55 (after $AA)

0x2003

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