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L9662 bảng dữ liệu(PDF) 55 Page - STMicroelectronics |
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L9662 bảng dữ liệu(HTML) 55 Page - STMicroelectronics |
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55 / 80 page ![]() DocID028325 Rev 1 55/80 L9662 Functional description 79 3.4.6 Satellite sensor interface The device provides four currents limited to I_Lim each through outputs ICH1, ICH2, ICH3 and ICH4. The voltage at these four channels is supplied by the VSATS input. Channels 1, 2, 3 and 4 serve as switched power sources to remote mounted satellite sensors. The device will monitor the current flow from its output pin and “demodulate” the current to be decoded using Manchester protocol. Decoded satellite message is communicated to an external microprocessor via SPI2. Both the satellite and squib circuits can be reset over when sending the appropriate configuration commands via SPI1 (16 bit SPI). For operation using a sync pulse a capacitor between 10 nF to 47 nF is required to be within 70 nH of the respective ASIC pin for signal stability. In case of loss of VCC all outputs will remain off. Satellite operation modes Each receiver channel provides different modes of operation that can be programmed by SPI command. Receive mode (asynchronous data transfer) In Receive Mode the sensor interface operates in asynchronous mode. The specified data messages from each channel will be continuously received every tasync. (Design Information only). The Sensor Interface supplies satellites and receives current modulated data. In this mode, the channels are supplied via pin VSATS. A voltage VICHxmin+Vhdp_max(I=75mA@105°C) at this input pin is required to provide the regulated voltage of VICHxmin at the satellite outputs [ICH0]...[ICH3]. Table 32. MOSI monitor mode 3 bit definition Bit MOSI command MISO response State Description D15 1 Mode Bits See above for state D14 1 See above for state D13 Odd Parity – Includes all 16 bits Odd Parity – Includes all 16 bits D12 0 See above for state D11 1 Mode selection See above for state D10 1 Mode selection See above for state D9-D6 ‘0001’ shall be device L9662 D5:D0 0 Revision Information: Upper 3 bits will reflect full pass Lower 3 bits will reflect metal/minor change First pass device will be indicated as “001 000” |
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