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L9662 bảng dữ liệu(PDF) 74 Page - STMicroelectronics |
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L9662 bảng dữ liệu(HTML) 74 Page - STMicroelectronics |
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74 / 80 page ![]() Functional description L9662 74/80 DocID028325 Rev 1 Status registers (SR) The definition for the Status Register is valid for all four protocols. The SR will always be the 1st word in the message of the MOSI frame The message faults and data/channel information are indicated using 3 bits per channel (SF2, SF1 and SF0). These bits represent the actual highest priority state of the ICHx- receiver, i.e. any change in a state will overwrite the previous value with the highest priority fault being reported if more than one fault exists. The following describes the bit usage Bit [D15] If during the previous received request a SPI communication error occurred or invalid message was received, the device shall set bit D15 and this means that the whole data frame of 80 bit is not valid. Bits [D13:D02] Fault Codes Definition Supporting Satellite Interface, Hall Effect, and raw data modes 0 1 1 17.10/20.90 1 0 0 20.25/24.75 1 0 1 24.85/29.15 1 1 0 28.80/34.20 1 1 1 35.10/42.90 Table 45. Current range supported D2 D1 D0 Current Threshold (mA) min/max Command/ Mode from Master MOSI Bit Definition D15 D14 D13 D12 D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00 MOSI Command 0 1 0 0 0 0 0 0 0000 0 0 0 odd MISO Response SR SPI ERR 1 CH4 SF2 CH4 SF1 CH4 SF0 CH3 SF2 CH3 SF1 CH3 SF0 CH2S SF2 CH2S SF1 CH2S SF0 CH1S SF2 CH1 SF1 CH1 SF0 POR STAT odd Table 46. CCR D14 definition Priority CHxSF2 CHxSF1 CHxSF0 Description CCR D14=0 7 0 0 0 Good Data from satellite on word ‘x’ 6 0 0 1 Two or more good data received from satellite, i.e. there are some data lost. |
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