L9662 datasheet(65/80 Pages) STMICROELECTRONICS

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L9662

Functional description

3.4.7

SPI register definition for satellite functions

The SPI provides access to read/write to the registers internal to the device. All commands

sent to the ASIC shall use set D15 as required for odd parity on the 16 bit word. The total

message length when CS_S is active is 80 bits. The response to the command is sent in the

next valid CS_S.

The following diagram shows the satellite SPI transfer during normal operation. The satellite

data is uploaded based on CS_S going active. All the register data for the channels will be

loaded at the same time.

OFF

Data will reflect if ICHx current

is above/below threshold setting

(1)

D0 = 0 (above thres.)

D0 = 1 (below thres.)

Digital Output

Satellite Data

OFF (HiZ)

Satellite Data

OFF (HiZ)

Empty

Analog Output

(I_Sat/100)

Satellite Data

Digital Output

OFF

Empty

OFF (HiZ)

OFF

Empty

OFF (HiZ)

OFF

Empty

Analog Output

(I_Sat/100)

OFF

Empty

Digital Output

1. IFx/Vx Pin is set as Analog Output (I_Sat/100) but since ICHx is off (HiZ) the IFx/Vx output will look like it is HiZ

Table 33. MCR and CCR settings based on the interfacing to a sensor or satellite (continued)

Functions active

Information available

MCR

D7/D6

Bits

MCR

D5/D4

Bits

CCR

D5:D4

Bits

Channel

(ICHx)

Decoder

SPI

DATA register

IFx/Vx pin

Table 34. SPI register definition

Registers for satellite communication

Description

Module Configuration Register

MCR

Global configuration for all channels

Channel Configuration Registers

CCR1

CCR2

CCR3

CCR4

Used to configure individual channels and

receive

satellite information

Internal pointer incremented to each channel

Status Register

Status of channels

Channel leakage to ground/battery/open faults

Message faults (Start bits, Other)

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