L9662 datasheet(59/80 Pages) STMICROELECTRONICS

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L9662

Functional description

The device is capable of different bit rates, which can be programmed via SPI2 based on

the operating frequency of the satellite bus. For the first message and all subsequent

messages the ASIC uses the Start Bits’ time to decode the rest of the bits in the message. In

case the measured bit rate obtained using the 2 Start bits doesn’t fall within the range

selected by the SPI as defined the device declares a bit time error and waits for idle. The

idle time between messages is 1.5 times the measured start bits time of the previous

message unless a message error is detected. If an error is detected then the device shall

default to 1.5 times the maximum frequency (minimum bit time). The initial idle time (after a

POR or reset) is 0 bit times.

The decoder uses a counter to track the high to low and low to high transitions at the bit

center. Figure 15 is an example that illustrates how the ASIC performs the decoding.

A transition is considered a bit center only when an edge is detected 75% to 125% of the

reference bit time after de-glitch filter. The de-glitch filter can modify bit time if the noise on is

not symmetric on each transition. When a single edge occurs below 75% of the reference bit

time it is considered to be a bit edge but it is ignored. When the decoder detects a second

edge below 75% of the reference bit time the device declares a bit time error via SPI, revert

to the minimum bit time of the selected range, and wait for idle. When a valid bit center is

detected the counter will reset and start counting again until another edge is detected. If the

message is not complete and no edge is detected in the range of 75% to 125% of measured

bit time, the device declares a bit time error via SPI, revert to the minimum bit time of the

selected range, and wait for idle. The idle time is defined as 150% of the minimum bit time of

the selected protocol speed range. If there is no bit transition detected for that period of time

and the correct number of bits was received, the message is considered complete. Bit time

error and too many bits faults are stored directly into the data register once they are

selected without the need to wait till an idle time. Since a bit time error is reported directly

once it is detected before Idle time, too few bits error may never be reported since bit time

error is detected first.

Bit time errors and too many bits errors will cause the decoder to revert to the minimum bit

time of the selected range, and discard the message. In case of a message containing

multiple errors only one error code is reported per message, errors detected in the decoding

phase have the following reporting priority; bit time errors, too many bits errors then

communication errors (CRC/Parity).

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