L9662 datasheet(67/80 Pages) STMICROELECTRONICS

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L9662

Functional description

The MOSI input takes data from the master microprocessor while CS_S is asserted. The

MSB is the first bit of each word received on MOSI and the LSB is the last bit of each word

received on MOSI. This pin has TTL level compatible input voltages allowing proper

operation with microprocessors using a 3.3 to 5.0 volt supply.

When data is transmitted for any of the first 4 words on MISO then the SR will be the 5th

word. This is required to identify good vs. bad data since, depending on the data mode, all

16 bits from a satellite can be data.

Satellite module configuration register (MCR)

This register defines the global configuration to the satellite module.

The MCR will be the 1st word in the message of the MOSI transfer. The micro MUST never

write the MCR in the wrong position because it will be recognized by the ASIC as a CCR.

The SPI message definition for MOSI commands and MISO responses for the MCR are

defined below.

Command/

Mode

MOSI Bit Definition

D15 D14 D13

D12

D11

D10

D09

D08

D07

D06

D05

D04

D03 D02 D01

D00

MOSI Command

MCR

0 CH4P CH3P CH2P CH1P SPL1 SPL0 IV4EN IV3EN IV4SEL IV3SEL SW RD

odd

MISO Response

MCR

CH4P CH3P CH2P CH1P SPL

SPL IV4EN IV3EN IV4SEL IV3SEL SW RD

odd

Table 36. MOSI MCR bit definition

Bit

MOSI Command MS – Mode‘D3’=0

MOSI Command PSI5 – Mode‘D3’=1

State

Description

D15

D14

D13

CH3 Protocol A Mode (default)

CH3 Protocol B Mode

Not valid

PSI5 Parity

D12

CH2 Protocol A Mode (default)

CH2 Protocol B Mode

Not valid

PSI5 Parity

D11

CH1 Protocol A Mode (default)

CH1 Protocol B Mode

Not valid

PSI5 Parity

D10

CH0 Protocol A Mode (default)

CH0 Protocol B Mode

Not valid

PSI5 Parity

Sync Pulse length

Disable IF3/V3 pin (default)

Disable IF3/V3 pin (default) Enable IF3/V3 pin

Enable IF3/V3 pin

Disable IF2/V2 pin (default)

Disable IF3/V3 pin (default) Enable IF3/V3 pin

IF3/V3 Output Selection

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