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FXLS8471Q bảng dữ liệu(PDF) 64 Page - Freescale Semiconductor, Inc

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Giải thích chi tiết về linh kiện  Linear Accelerometer
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FXLS8471Q bảng dữ liệu(HTML) 64 Page - Freescale Semiconductor, Inc

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FXLS8471Q
Sensors
64
Freescale Semiconductor, Inc.
Therefore an ODR setting of 400 Hz, when accelerometer OSR is set to normal using CTRL_REG2, would result in a maximum
pulse-time limit of (0.625 ms * 255)
= 159 ms.
10.11.7
PULSE_LTCY (0x27) register
Minimum time step for the pulse latency is defined in Tables 134 and 135. Maximum time is “(time step @ ODR and power mode)
x 255”.
Table 131. Time step for PULSE_TMLT with HP_FILTER_CUTOFF[pls_hpf_en] = 0
ODR (Hz)
Max time range (s)
Time step (ms)
Normal
LPLN
High
resolution
Low power
Normal
LPLN
High
resolution
Low power
800
0.159
0.159
0.159
0.159
0.625
0.625
0.625
0.625
400
0.159
0.159
0.159
0.319
0.625
0.625
0.625
1.25
200
0.319
0.319
0.159
0.638
1.25
1.25
0.625
2.5
100
0.638
0.638
0.159
1.28
2.5
2.5
0.625
5
50
1.28
1.28
0.159
2.55
5
5
0.625
10
12.5
1.28
5.1
0.159
10.2
5
20
0.625
40
6.25
1.28
5.1
0.159
10.2
5
20
0.625
40
1.56
1.28
5.1
0.159
10.2
5
20
0.625
40
Table 132. PULSE_LTCY register
pls_ltcy[7:0]
8’b00000000
Table 133. PULSE_LTCY bit description
Field
Description
pls_ltcy[7:0]
pls_ltcy[7:0] defines the time interval that starts after the first pulse detection where the pulse-detection function ignores
the start of a new pulse.
Table 134. Time step for PULSE_LTCY with HP_FILTER_CUTOFF[pls_hpf_en] = 1
ODR (Hz)
Max time range (s)
Time step (ms)
Normal
LPLN
High
resolution
Low power
Normal
LPLN
High
resolution
Low power
800
0.638
0.638
0.638
0.638
2.5
2.5
2.5
2.5
400
1.276
1.276
1.276
1.276
5
5
5
5
200
2.56
2.56
1.276
2.56
10
10
5
10
100
5.1
5.1
1.276
5.1
20
20
5
20
50
10.2
10.2
1.276
10.2
40
40
5
40
12.5
10.2
40.8
1.276
40.8
40
160
5
160
6.25
10.2
40.8
1.276
81.6
40
160
5
320
1.56
10.2
40.8
1.276
81.6
40
160
5
320



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