FXLS8471Q datasheet(31/75 Pages) FREESCALE

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FXLS8471Q

Sensors

Freescale Semiconductor, Inc.

10.1.6

INT_SOURCE (0x0C) register

Interrupt source register. The bits that are set (logic ‘1’) indicate which function has asserted its interrupt and conversely bits that

are cleared (logic ‘0’) indicate which function has not asserted its interrupt.

Reading the INT_SOURCE register does not clear any interrupt status bits (except for src_a_vecm, see below); the respective

interrupt flag bits are reset by reading the appropriate source register for the function that generated the interrupt.

Table 25. INT_SOURCE register

src_aslp

src_fifo

src_trans

src_lndprt

src_pulse

src_ffmt

src_a_vecm

src_drdy

Table 26. INT_SOURCE bit descriptions

Field

Description

src_aslp

Auto-Sleep/Wake interrupt status bit: logic ‘1’ indicates that an interrupt event that can cause a Wake to Sleep or Sleep to

Wake system mode transition has occurred and logic ‘0’ indicates that no Wake to Sleep or Sleep to Wake system mode

transition interrupt event has occurred.

The “Wake-to-Sleep” transition occurs when a period of inactivity that exceeds the user-specified time limit

(ASLP_COUNT) has been detected, thus causing the system to transition to a user-specified low ODR setting.

A “Sleep-to-Wake” transition occurs when the user-specified interrupt event has awakened the system, thus causing the

system to transition to the user-specified higher ODR setting.

Reading the SYSMOD register will clear the src_aslp bit.

src_fifo

FIFO interrupt status bit: logic ‘1’ indicates that a FIFO interrupt event such as an overflow or watermark (F_STATUS[f_cnt]

= F_STATUS[f_wmrk]) event has occurred and logic ‘0’ indicates that no FIFO interrupt event has occurred.

This bit is cleared by reading the F_STATUS register.

src_trans

Transient interrupt status bit: logic ‘1’ indicates that an acceleration transient value greater than user-specified threshold

has occurred. and logic ‘0’ indicates that no transient event has occurred.

This bit is asserted whenever TRANSIENT_SRC[ea] is asserted and the functional block interrupt has been enabled.

This bit is cleared by reading the TRANSIENT_SRC register.

src_lndprt

Landscape/Portrait orientation interrupt status bit: logic ‘1’ indicates that an interrupt was generated due to a change in the

device orientation status and logic ‘0’ indicates that no change in orientation status was detected.

This bit is asserted whenever PL_STATUS[newlp] is asserted and the functional block interrupt has been enabled.

This bit is cleared by reading the PL_STATUS register.

src_pulse

Pulse interrupt status bit: logic ‘1’ indicates that an interrupt was generated due to single- and/or double- pulse event and

logic ‘0’ indicates that no pulse event was detected.

This bit is asserted whenever PULSE_SRC[ea] is asserted and the functional block interrupt has been enabled.

This bit is cleared by reading the PULSE_SRC register.

src_ffmt

Freefall/motion interrupt status bit: logic ‘1’ indicates that the freefall/motion function interrupt is active and logic ‘0’

indicates that no freefall or motion event was detected.

This bit is asserted whenever PULSE_SRC[ea] is asserted and the functional block interrupt has been enabled.

This bit is cleared by reading the A_FFMT_SRC register.

src_a_vecm

Accelerometer vector-magnitude interrupt status bit: logic ‘1’ indicates that an interrupt was generated due to acceleration

vector-magnitude function and logic ‘0’ indicates that no interrupt has been generated. This bit is cleared by reading this

src_drdy

Data-ready interrupt status bit. In acceleration only mode this bit indicates that new accelerometer data is available to read.

The src_drdy interrupt flag is cleared by reading out the acceleration data from the OUT_X, OUT_Y, and OUT_Z registers.

This data can be burst read using a 6-byte burst read starting from the address 0x01 (OUT_X_MSB).

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