FXLS8471Q datasheet(6/75 Pages) FREESCALE

6 / 75 page

FXLS8471Q

Sensors

Freescale Semiconductor, Inc.

Pin Description

Figure 2. Pinout diagram

Device power is supplied through the VDD pin. Power-supply, decoupling capacitors (100 nF ceramic plus 4.7

μF or larger bulk)

should be placed as close as possible to pin 14 of the device. The digital interface supply voltage (VDDIO) must also be

decoupled with a 100 nF ceramic capacitor placed as close as possible to pin 1 of the device.

The digital control signals SCL, SDA, SA0, SA1, and RST are not tolerant of voltages more than VDDIO + 0.3 V. If VDDIO is

removed, these pins will clamp any logic signals through their internal ESD protection diodes.

Table 1. Pin Description

Name

Function

VDDIO

Interface power supply

BYP

Internal regulator output bypass capacitor connection

Reserved

Test reserved, connect to GND

4SCL/SCLK

I2C Serial Clock/SPI Clock

GND

Ground

6SDA/MOSI

I2C Serial Data/SPI Master Out, Slave In

SA0/MISO(1)

1. The SA0 pin is also used to select the desired serial interface mode during POR and also after a hard/soft reset event. Please see

Section 6.2.3, “I2C/SPI auto detection” for more information

I2C address selection bit 0/SPI Master In, Slave Out

N/C

Internally not connected

INT2

Interrupt 2

SA1/CS_B

I2C address selection bit 1(2)/SPI Chip Select (active low)

2. See Table 8 for I2C address options selectable using the SA0 and SA1 pins.

INT1

Interrupt 1

GND

Ground

Reserved

Test reserved, connect to GND

VDD

Power supply

N/C

Internally not connected

RST

Reset input, active high. Connect to GND if unused

VDDIO

BYP

Reserved

SCL/SCLK

GND

Reserved

GND

INT1

SA1/CS_B

INT2

Top View

16 Lead QFN-COL

3 mm x 3 mm x 1 mm

FXLS8471Q

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