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FXLS8471Q bảng dữ liệu(PDF) 38 Page - Freescale Semiconductor, Inc |
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FXLS8471Q bảng dữ liệu(HTML) 38 Page - Freescale Semiconductor, Inc |
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38 / 75 page ![]() FXLS8471Q Sensors 38 Freescale Semiconductor, Inc. Figure 10. Interrupt controller block diagram The system’s interrupt controller uses the corresponding bit field in the CTRL_REG5 register to determine the routing for the INT1 and INT2 interrupt pins. For example, if the int_cfg_drdy bit value is logic ‘0’ the functional block’s interrupt is routed to INT2, and if the bit value is logic ‘1’ then the interrupt is routed to INT1. All interrupt signals routed to either INT1 or INT2 are logically OR’ed together as illustrated in Figure 11, thus one or more functional blocks can assert an interrupt pin simultaneously; therefore a host application responding to an interrupt should read the INT_SOURCE register to determine the source(s) of the interrupt(s). Figure 11. INT1/INT2 PIN Control Logic INTERRUPT CONTROLLER Data Ready Freefall/Motion Detection Pulse Detection Orientation Detection Transient Acceleration Detection Auto-Sleep INT ENABLE INT CFG INT1 INT2 99 Acceleration Vector-magnitude FIFO Interrupt INT1 INT2 SRC_RTS SRC_FIFO SRC_PULSE SRC_FF_MT OR OR SRC_DRDY |
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