FXLS8471Q datasheet(27/75 Pages) FREESCALE

27 / 75 page

FXLS8471Q

Sensors

Freescale Semiconductor, Inc.

NOTE

The auto-increment addressing is only enabled when registers are read using burst-read mode when the device is configured for

I2C or SPI. The auto-increment address is automatically reset to 0x00 in I2C mode when a stop condition is detected. In SPI mode

there is no stop condition and the auto-increment address is not automatically reset to 0x00.

A_VECM_THS_LSB

R/W

0x61

0x62

0x00

Acceleration vector-

magnitude threshold

LSB

A_VECM_CNT

R/W

0x62

0x63

0x00

Acceleration vector-

magnitude debounce

count

A_VECM_INITX_MSB

R/W

0x63

0x64

0x00

Acceleration vector-

magnitude X-axis

reference value MSB

A_VECM_INITX_LSB

R/W

0x64

0x65

0x00

Acceleration vector-

magnitude X-axis

reference value LSB

A_VECM_INITY_MSB

R/W

0x65

0x66

0x00

Acceleration vector-

magnitude Y-axis

reference value MSB

A_VECM_INITY_LSB

R/W

0x66

0x67

0x00

Acceleration vector-

magnitude Y-axis

reference value LSB

A_VECM_INITZ_MSB

R/W

0x67

0x68

0x00

Acceleration vector-

magnitude Z-axis

reference value MSB

A_VECM_INITZ_LSB

R/W

0x68

0x69

0x00

Acceleration vector-

magnitude Z-axis

reference value LSB

Reserved

—

0x69-

0x72

—

Reserved, do not modify

A_FFMT_THS_X_MSB

R/W

0x73

0x74

0x00

X-axis FMT threshold

MSB

A_FFMT_THS_X_LSB

R/W

0x74

0x75

0x00

X-axis FFMT threshold

LSB

A_FFMT_THS_Y_MSB

R/W

0x75

0x76

0x00

Y-axis FFMT threshold

MSB

A_FFMT_THS_Y_LSB

R/W

0x76

0x77

0x00

Y-axis FFMT threshold

LSB

A_FFMT_THS_Z_MSB

R/W

0x77

0x78

0x00

Z-axis FFMT threshold

MSB

A_FFMT_THS_Z_LSB

R/W

0x78

0x79

0x00

Z-axis FFMT threshold

LSB

Reserved

—

0x79 -

0xFF

—

Reserved, do not modify

1. Register contents are preserved when transitioning from Active to Standby mode.

2. Register contents are reset when transitioning from Standby to Active mode.

3. Register contents can be modified anytime in Standby or Active mode. A write to this register will cause a reset of the corresponding internal

system debounce counter.

4. Modification of this register’s contents can only occur when device is in Standby mode, except the FS[1:0] bit fields in CTRL_REG1 register.

Table 13. Register Address Map

(Continued)

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