PM0056 datasheet(107/156 Pages) STMICROELECTRONICS

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PM0056

Core peripherals

Table 36 shows the cache policy for memory attribute encodings with a TEX value is in the

range 4-7.

Table 37 shows the AP encodings that define the access permissions for privileged and

unprivileged software.

Table 35. TEX, C, B, and S encoding

TEX

Memory type

Shareability

Other attributes

b000

0x (1) Strongly-ordered

Shareable

x(1) Device

Shareable

Normal

Not shareable Outer and inner write-through. No

write allocate.

Shareable

Normal

Not shareable Outer and inner write-back. No write

allocate.

Shareable

b001

Normal

Not shareable

Outer and inner Non-cacheable.

Shareable

x(1) Reserved encoding

x(1)

Implementation defined

attributes.

Normal

Not shareable Outer and inner write-back. Write

and read allocate.

Shareable

b010

x(1) Device

Not shareable Non-shared Device.

x(1) Reserved encoding

1x(1)

x(1) Reserved encoding

b1BB

Normal

Not shareable Cached memory(2), BB = outer

policy, AA = inner policy.

Shareable

1. THe MPU ignores the value for this bit.

2. See Table 36 for the encoding of the AA and BB bits.

Table 36. Cache policy for memory attribute encoding

Encoding, AA or BB

Corresponding cache policy

Non-cacheable

Write back, write and read allocate

Write through, no write allocate

Write back, no write allocate

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