AT89LP51RB2 datasheet(51/254 Pages) ATMEL

51 / 254 page

3722A–MICRO–10/11

AT89LP51RB2/RC2/IC2 Preliminary

Reset

During reset, all I/O Registers are set to their initial values, the port pins are set to their default

mod e , a nd the pr ogr a m st a rt s e x ec u t i on fr om t he Reset Vect or , 0 000 H. The

AT89LP51RB2/RC2/IC2 has six sources of reset: power-on reset, brown-out reset, external

reset, hardware watchdog reset, PCA watchdog reset and software reset.

Figure 7-1.

Reset Subsystem Diagram

7.1

Power-on Reset

A Power-on Reset (POR) is generated by an on-chip detection circuit. The detection level V

POR

is nominally 1.4V. The POR is activated whenever V

DD is below the detection level. The POR cir-

cuit can be used to trigger the start-up reset or to detect a major supply voltage failure. The POR

circuit ensures that the device is reset from power-on. A power-on sequence is shown in Figure

7-2. When V

DD reaches the Power-on Reset threshold voltage VPOR, an initialization sequence

lasting t

POR is started. When the initialization sequence completes, the start-up timer determines

how long the device is kept in POR after V

DD rise. The start-up timer does not begin counting

until after V

DD reaches the Brown-out Detector (BOD) threshold voltage VBOD. The POR signal is

activated again, without any delay, when V

DD falls below the POR threshold level. A Power-on

Reset (i.e. a cold reset) will set the POF flag in PCON. The internally generated reset can be

extended beyond the power-on period by holding the RST pin active longer than the time-out.

The start-up timer delay is user-configurable with the Start-up Time User Fuses and depends on

the clock source (Table 7-1). The Start-Up Time fuses also control the length of the start-up time

after a Brown-out Reset or when waking up from Power-down during internally timed mode. The

start-up delay should be selected to provide enough settling time for V

DD and the selected clock

source. The device operating environment (supply voltage, frequency, temperature, etc.) must

meet the minimum system requirements before the device exits reset and starts normal opera-

tion. The RST pin may be held active externally until these conditions are met.

While the POR is active a reset output pulse will be generated on the RST pin to reset the board-

level circuitry. The output pulse is either open-drain or open-source as shown in Figure 7-4. In

order to properly propagate this pulse to the rest of the board in the case of an external capacitor

or power-supply supervisor circuit, a 1 k

Ω resistor should be placed in series with any external

driving circuitry as shown in Figure 7-5. The POR output pulse cannot be disabled.

POR

BOD

DISRTO

RST

Internal Reset

Hardware

Watchdog

PCA

Watchdog

Software

Reset

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