AT89LP51RB2 datasheet(77/254 Pages) ATMEL

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3722A–MICRO–10/11

AT89LP51RB2/RC2/IC2 Preliminary

13. Enhanced Timer 0 and Timer 1 with PWM

The AT89LP51RB2/RC2/IC2 has two 16-bit Timer/Counters, Timer 0 and Timer 1, with the fol-

lowing features:

• Two 16-bit timer/counters with 16-bit reload registers

• Two independent 8-bit precision PWM outputs with 8-bit prescalers

•UART or SPI baud rate generation using Timer 1

•Output pin toggle on timer overflow

• Split timer mode allows for three separate timers (2 8-bit, 1 16-bit)

•Gated modes allow timers to run/halt based on an external input

Timer 0 and Timer 1 have similar modes of operation. As timers, the timer registers normally

increase every clock cycle. Thus, the registers count clock cycles. The timer rate can be pres-

caled by a value between 1 and 16 using the Timer Prescaler (see Section 6.9 on page 48).

Both Timers share the same prescaler. In Compatibility mode the prescaler is always enabled

and TPS defaults to 5, so the timers count every six clock cycles (1/12 of the oscillator frequency

in X1 mode or 1/6 of the oscillator frequency in X2 mode). In X2 mode the timers can be set to

the X1 rate by setting the T0X2 or T1X2 bits in CKCON1. In Fast mode the prescaler is not

enabled by default so the count rate is equal to the system frequency (1/2 of the oscillator fre-

quency in X1 mode or equal to the oscillator frequency in X2 mode). In this case setting the

T0X2 or T1X2 bits in CKCON1 enables the prescaler for each timer.

As counters, the timer registers are incremented in response to a 1-to-0 transition at the corre-

sponding input pins, T0 or T1. In Fast mode the external input is sampled every clock cycle.

When the samples show a high in one cycle and a low in the next cycle, the count is incre-

mented. The new count value appears in the register during the cycle following the one in which

the transition was detected. Since 2 clock cycles are required to recognize a 1-to-0 transition,

the maximum count rate is 1/2 of the system frequency. There are no restrictions on the duty

cycle of the input signal, but it should be held for at least one full clock cycle to ensure that a

given level is sampled at least once before it changes.

In Compatibility mode the counter input sampling is controlled by the prescaler. Since TPS

defaults to 6 in this mode, the pins are sampled every six system clocks. Therefore the input sig-

nal should be held for at least six clock cycles to ensure that a given level is sampled at least

once before it changes.

Furthermore, the Timer or Counter functions for Timer 0 and Timer 1 have four operating modes:

13-bit timer, 16-bit timer, 8-bit auto-reload timer, and split timer. The control bits C/T in the Spe-

cial Function Register TMOD select the Timer or Counter function. The bit pairs (M1, M0) in

TMOD select the operating modes.

fTIMER

fSYS

TnX2

TPS

()

------------------------------------------------

Compatibility Mode

TIMER

SYS

TPS

---------------------

Fast Mode and TnX2 = 1

fTIMER

fSYS

Fast Mode and TnX2 = 0

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