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AT89LP51RB2 bảng dữ liệu(PDF) 92 Page - ATMEL Corporation |
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AT89LP51RB2 bảng dữ liệu(HTML) 92 Page - ATMEL Corporation |
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92 / 254 page ![]() 92 3722A–MICRO–10/11 AT89LP51RB2/RC2/IC2 Preliminary Figure 14-3. Timer 2 Waveform: Auto-Reload Mode (DCEN = 0) 14.3.2 Up or Down Counter Setting DCEN = 1 enables Timer 2 to count up or down, as shown in Figure 14-5. In this mode, the T2EX pin controls the direction of the count (if EXEN2 = 1). A logic 1 at T2EX makes Timer 2 count up. When T2CM 1-0 = 00B, the timer will overflow at MAX and set the TF2 bit. This overflow also causes BOTTOM, the 16-bit value in RCAP2H and RCAP2L, to be reloaded into the timer registers, TH2 and TL2, respectively. A logic 0 at T2EX makes Timer 2 count down. The timer underflows when TH2 and TL2 equal BOTTOM, the 16-bit value stored in RCAP2H and RCAP2L. The underflow sets the TF2 bit and causes MAX to be reloaded into the timer regis- ters. The EXF2 bit toggles whenever Timer 2 overflows or underflows and can be used as a 17th bit of resolution. In this operating mode, EXF2 does not flag an interrupt. The behavior of Timer 2 when DCEN is enabled is shown in Figure 14-4. The timer over- flow/underflow rate for up-down counting mode is the same as for up counting mode, provided that the count direction does not change. Changes to the count direction may result in longer or shorter periods between time-outs. Figure 14-4. Timer 2 Waveform: Auto-Reload Mode (DCEN = 1) MAX MIN BOTTOM TF2 Set MAX MIN BOTTOM T2EX TF2 Set EXF2 |
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