AT89LP51RB2 datasheet(89/254 Pages) ATMEL

89 / 254 page

3722A–MICRO–10/11

AT89LP51RB2/RC2/IC2 Preliminary

14.1

Timer 2 Registers

Control and status bits for Timer 2 are contained in registers T2CON (see Table 14-3) and

T2MOD (see Table 14-4). The register pair {TH2, TL2} at addresses 0CDH and 0CCH are the

16-bit timer register for Timer 2. The register pair {RCAP2H, RCAP2L} at addresses 0CBH and

0CAH are the 16-bit Capture/Reload register for Timer 2 in capture and auto-reload modes.

Note:

The Timer 2 operating mode depends on bits in both T2CON and T2MOD as shown in Table 14-1. The RCLK, TCLK and T2OE

bits have priority over CP/RL2.

Table 14-3.

T2CON – Timer/Counter 2 Control Register

T2CON Address = 0C8H

Reset Value = 0000 0000B

Bit Addressable

TF2

EXF2

RCLK

TCLK

EXEN2

TR2

C/T2

CP/RL2

Bit

654

321

Symbol

Function

TF2

Timer 2 Overflow Flag

Set by hardware when Timer 2 overflows and must be cleared by software. TF2 will not be set when either

RCLK = 1 or TCLK = 1. TF2 will generate an interrupt when ET2 is set in IEN0.

EXF2

Timer 2 External Flag

Set when either a capture or reload is caused by a negative transition on T2EX and EXEN2 = 1. When Timer 2 interrupt is

enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2 interrupt routine. EXF2 must be cleared by software. EXF2

does not cause an interrupt in up/down counter mode (DCEN = 1) or dual-slope mode.

RCLK

Receive Clock Enable

Set to use Timer 2 overflow pulses for receive clock in serial port Modes 1 and 3. Clear to use Timer 1 overflows for the

receive clock.

TCLK

Transmit Clock Enable

Set to use Timer 2 overflow pulses for transmit clock in serial port Modes 1 and 3. Clear to use Timer 1 overflows for the

transmit clock.

EXEN2

Timer 2 External Enable

When set, allows a capture or reload to occur as a result of a negative transition on T2EX if Timer 2 is not being used to

clock the serial port. EXEN2 = 0 causes Timer 2 to ignore events at T2EX.

TR2

Timer 2 Run Control

Start/Stop control for Timer 2. TR2 = 1 starts the timer. TR2 = 0 stops the timer.

C/T2

Timer/Counter Select 2

Clear C/T2 = 0 for timer function. Set C/T2 = 1 for external event counter on T2 (P1.0) (falling edge triggered). C/T2 must

be 0 to use clock out mode.

CP/RL2

Capture/Reload Select

CP/RL2 = 1 causes captures to occur on negative transitions at T2EX if EXEN2 = 1. CP/RL2 = 0 causes automatic

reloads to occur when Timer 2 overflows or negative transitions occur at T2EX when EXEN2 = 1. When either RCLK or

TCLK = 1, this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow.

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