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AT89LP51RB2 bảng dữ liệu(PDF) 49 Page - ATMEL Corporation |
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AT89LP51RB2 bảng dữ liệu(HTML) 49 Page - ATMEL Corporation |
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49 / 254 page ![]() 49 3722A–MICRO–10/11 AT89LP51RB2/RC2/IC2 Preliminary Figure 6-7. Peripheral Clock Selection SIX2 UART Clock. In Compatibility Mode, clear for one system clock period per peripheral clock cycle and set for two clock periods per peripheral clock cycle (only valid when X2 = 1). In Fast Mode, clear for one system clock period and set for TPS+1 clocks per peripheral clock cycle. This bit affects the generated baud rate during modes 0 and 2. T2X2 Timer 2 Clock. In Compatibility Mode, clear for TPS+1 system clock periods per peripheral clock cycle and set for 2(TPS+1) clock periods per peripheral clock cycle. In Fast Mode, clear for one system clock period and set for TPS+1 clocks per peripheral clock cycle. This bit affects the timer increment/decrement rate. T1X2 Timer 1 Clock. In Compatibility Mode, clear for TPS+1 system clock periods per peripheral clock cycle and set for 2(TPS+1) clock periods per peripheral clock cycle. In Fast Mode, clear for one system clock period and set for TPS+1 clocks per peripheral clock cycle. This bit affects the timer increment rate. T0X2 Timer 0 Clock. In Compatibility Mode, clear for TPS+1 system clock periods per peripheral clock cycle and set for 2(TPS+1) clock periods per peripheral clock cycle. In Fast Mode, clear for one system clock period and set for TPS+1 clocks per peripheral clock cycle. This bit affects the timer increment rate. X2 CPU Clock. In Compatibility Mode, clear for 12 clock periods per machine cycle and set for 6 clock periods per machine cycle. In Fast Mode, clear for two clock periods per instruction cycle and set for one clock periods per instruction cycle. The default state of X2 is set by the X2 Fuse. See Section 24.2 on page 188. Symbol Function SYSTEM CLOCK ÷2 0 1 T0X2 ÷(TPS+1) Timer 0 ÷2 0 1 Timer 1 T1X2 0 1 Timer 2 T2X2 0 1 Watchdog WDX2 0 1 PCA (CPS = 00B) PCAX2 0 1 PCA (CPS = 01B) PCAX2 SIX2 & X2 UART 0 1 SPIX2 & X2 SPI 0 1 TWIX2 & X2 TWI 0 1 SYSTEM CLOCK 0 1 T0X2 ÷(TPS+1) Timer 0 ÷2 0 1 Timer 1 T1X2 0 1 Timer 2 T2X2 0 1 Watchdog WDX2 0 1 PCA (CPS = 00B) PCAX2 0 1 PCA (CPS = 01B) PCAX2 SIX2 & X2 UART 0 1 SPIX2 & X2 SPI 0 1 TWIX2 & X2 TWI 0 1 Fast Mode Compatibility Mode |
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