AT89LP51RB2 datasheet(88/254 Pages) ATMEL

88 / 254 page

3722A–MICRO–10/11

AT89LP51RB2/RC2/IC2 Preliminary

Note:

In Fast Mode, TPS applies only when the T2X2 bit in CKCON0 is set. TPS always

applies in Compatibility Mode, therefore setting T2X2 in Compatibility Mode will halve

the timer frequency.

In the Counter function, the register is incremented in response to a 1-to-0 transition at its corre-

sponding external input pin, T2. In Fast mode the external input is sampled every clock cycle.

When the samples show a high in one cycle and a low in the next cycle, the count is incre-

mented. The new count value appears in the register during the cycle following the one in which

the transition was detected. Since 2 clock cycles are required to recognize a 1-to-0 transition,

the maximum count rate is 1/2 of the system frequency. There are no restrictions on the duty

cycle of the input signal, but it should be held for at least one full clock cycle to ensure that a

given level is sampled at least once before it changes.

In Compatibility mode the counter input sampling is controlled by the prescaler. Since TPS

defaults to 6 in this mode, the pins are sampled every six system clocks. Therefore the input sig-

nal should be held for at least six clock cycles to ensure that a given level is sampled at least

once before it changes.

The following definitions for Timer 2 are used in the subsequent paragraphs:

Table 14-1.

Timer 2 Operating Modes

RCLK + TCLK

CP/RL2

DCEN

T2OE

TR2

MODE

16-bit Auto-reload

16-bit Auto-reload Up-Down

16-bit Capture

XXX

Baud Rate Generator

Frequency Generator

(Off)

Table 14-2.

Timer 2 Definitions

Symbol

Definition

MIN

0000H

MAX

FFFFH

BOTTOM

16-bit value of {RCAP2H,RCAP2L}

fTIMER

SYS

T2X2

TPS

()

------------------------------------------------

Compatibility Mode

fTIMER

fSYS

TPS

---------------------

Fast Mode and T2X2 = 1

TIMER

SYS

Fast Mode and T2X2 = 0

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