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PIC18F2680ISPSQTP bảng dữ liệu(PDF) 387 Page - Microchip Technology

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Giải thích chi tiết về linh kiện  PIC18F2585/2680/4585/4680 Data Sheet
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nhà sản xuất  MICROCHIP [Microchip Technology]
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© 2007 Microchip Technology Inc.
Preliminary
DS39625C-page 385
PIC18F2585/2680/4585/4680
LFSR
Load FSR
Syntax:
LFSR f, k
Operands:
0
≤ f ≤ 2
0
≤ k ≤ 4095
Operation:
k
→ FSRf
Status Affected:
None
Encoding:
1110
1111
1110
0000
00ff
k7kkk
k11kkk
kkkk
Description:
The 12-bit literal ‘k’ is loaded into the
file select register pointed to by ‘f’.
Words:
2
Cycles:
2
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read literal
‘k’ MSB
Process
Data
Write
literal ‘k’
MSB to
FSRfH
Decode
Read literal
‘k’ LSB
Process
Data
Write literal
‘k’ to FSRfL
Example:
LFSR 2, 3ABh
After Instruction
FSR2H
=
03h
FSR2L
=
ABh
MOVF
Move f
Syntax:
MOVF
f {,d {,a}}
Operands:
0
≤ f ≤ 255
d
∈ [0,1]
a
∈ [0,1]
Operation:
f
→ dest
Status Affected:
N, Z
Encoding:
0101
00da
ffff
ffff
Description:
The contents of register ‘f’ are moved to
a destination dependent upon the
status of ‘d’. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
Location ‘f’ can be anywhere in the
256-byte bank.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f
≤ 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write W
Example:
MOVF
REG, 0, 0
Before Instruction
REG
=
22h
W=
FFh
After Instruction
REG
=
22h
W
=
22h



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