PIC18F2680ISPSQTP datasheet(383/482 Pages) MICROCHIP

383 / 482 page

Preliminary

DS39625C-page 381

PIC18F2585/2680/4585/4680

DECFSZ

Decrement f, Skip if 0

Syntax:

DECFSZ f {,d {,a}}

Operands:

≤ f ≤ 255

∈ [0,1]

Operation:

(f) – 1

→ dest,

skip if result = 0

Status Affected:

None

Encoding:

0010

11da

ffff

Description:

The contents of register ‘f’ are

decremented. If ‘d’ is ‘0’, the result is

placed in W. If ‘d’ is ‘1’, the result is

placed back in register ‘f’ (default).

If the result is ‘0’, the next instruction

which is already fetched is discarded

and a NOP is executed instead, making

it a two-cycle instruction.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f

≤ 95 (5Fh). See

Section 25.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words:

Cycles:

1(2)

Note:

3 cycles if skip and followed

by a 2-word instruction.

Q Cycle Activity:

Decode

Read

Process

Data

Write to

destination

If skip:

operation

If skip and followed by 2-word instruction:

operation

Example:

HERE

DECFSZ

CNT, 1, 1

GOTO

LOOP

CONTINUE

Before Instruction

Address (HERE)

After Instruction

CNT

CNT – 1

If CNT

PC =

Address (CONTINUE)

If CNT

≠

PC =

Address (HERE + 2)

DCFSNZ

Decrement f, Skip if not 0

Syntax:

DCFSNZ

f {,d {,a}}

Operands:

≤ f ≤ 255

∈ [0,1]

Operation:

(f) – 1

→ dest,

skip if result

≠ 0

Status Affected:

None

Encoding:

0100

11da

ffff

Description:

The contents of register ‘f’ are

decremented. If ‘d’ is ‘0’, the result is

placed in W. If ‘d’ is ‘1’, the result is

placed back in register ‘f’ (default).

If the result is not ‘0’, the next

instruction which is already fetched is

discarded and a NOP is executed

instead, making it a two-cycle

instruction.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f

≤ 95 (5Fh). See

Section 25.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words:

Cycles:

1(2)

Note:

3 cycles if skip and followed

by a 2-word instruction.

Q Cycle Activity:

Decode

Read

Process

Data

Write to

destination

If skip:

operation

If skip and followed by 2-word instruction:

operation

Example:

HERE

DCFSNZ

TEMP, 1, 0

ZERO

NZERO

Before Instruction

TEMP

After Instruction

TEMP

TEMP – 1,

If TEMP

Address (ZERO)

If TEMP

≠

Address (NZERO)

PIC18F2680ISPSQTP bảng dữ liệu(PDF) 383 Page - Microchip Technology

PIC18F2680ISPSQTP bảng dữ liệu(HTML) 383 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL