PIC18F2680ISPSQTP datasheet(356/482 Pages) MICROCHIP

356 / 482 page

PIC18F2585/2680/4585/4680

DS39625C-page 354

Preliminary

24.3

Two-Speed Start-up

The Two-Speed Start-up feature helps to minimize the

latency period from oscillator start-up to code execution

by allowing the microcontroller to use the INTRC

oscillator as a clock source until the primary clock

source is available. It is enabled by setting the IESO

Configuration bit.

Two-Speed Start-up should be enabled only if the

primary oscillator mode is LP, XT, HS or HSPLL

(Crystal-based modes). Other sources do not require

an OST start-up delay; for these, Two-Speed Start-up

should be disabled.

When enabled, Resets and wake-ups from Sleep mode

cause the device to configure itself to run from the

internal oscillator block as the clock source, following

the time-out of the Power-up Timer after a Power-on

Reset is enabled. This allows almost immediate code

execution while the primary oscillator starts and the

OST is running. Once the OST times out, the device

automatically switches to PRI_RUN mode.

Because the OSCCON register is cleared on Reset

events, the INTOSC (or postscaler) clock source is not

initially available after a Reset event; the INTRC clock

is used directly at its base frequency. To use a higher

clock speed on wake-up, the INTOSC or postscaler

clock sources can be selected to provide a higher clock

speed by setting bits, IRCF2:IRCF0, immediately after

Reset. For wake-ups from Sleep, the INTOSC or

postscaler clock sources can be selected by setting the

IRCF2:IRCF0 bits prior to entering Sleep mode.

In all other power managed modes, Two-Speed Start-up

is not used. The device will be clocked by the currently

selected clock source until the primary clock source

becomes available. The setting of the IESO bit is

ignored.

24.3.1

SPECIAL CONSIDERATIONS FOR

USING TWO-SPEED START-UP

While using the INTRC oscillator in Two-Speed Start-up,

the device still obeys the normal command sequences

for entering power managed modes, including serial

SLEEP

instructions (refer to Section 3.1.4 “Multiple

Sleep Commands”). In practice, this means that user

code can change the SCS1:SCS0 bit settings or issue

SLEEP

instructions before the OST times out. This would

allow an application to briefly wake-up, perform routine

“housekeeping” tasks and return to Sleep before the

device starts to operate from the primary oscillator.

User code can also check if the primary clock source is

currently providing the device clocking by checking the

status of the OSTS bit (OSCCON<3>). If the bit is set,

the primary oscillator is providing the clock. Otherwise,

the internal oscillator block is providing the clock during

wake-up from Reset or Sleep mode.

FIGURE 24-2:

TIMING TRANSITION FOR TWO-SPEED START-UP (INTOSC TO HSPLL)

Q3 Q4

OSC1

Peripheral

Program

PC + 2

INTOSC

PLL Clock

PC + 6

Output

CPU Clock

PC + 4

Clock

Counter

Note 1:

TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.

Wake from Interrupt Event

TPLL(1)

n-1

Clock

OSTS bit Set

Transition

Multiplexer

TOST(1)

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