PIC18F2680ISPSQTP datasheet(282/482 Pages) MICROCHIP

282 / 482 page

PIC18F2585/2680/4585/4680

DS39625C-page 280

Preliminary

ECANCON: ENHANCED CAN CONTROL REGISTER

R/W-0

R/W-1

R/W-0

MDSEL1(1) MDSEL0(1) FIFOWM(2)

EWIN4

EWIN3

EWIN2

EWIN1

EWIN0

bit 7

bit 0

bit 7-6

MDSEL1:MDSEL0: Mode Select bits(1)

= Legacy mode (Mode 0, default)

= Enhanced Legacy mode (Mode 1)

= Enhanced FIFO mode (Mode 2)

= Reserved

bit 5

FIFOWM: FIFO High Water Mark bit(2)

= Will cause FIFO interrupt when one receive buffer remains(3)

= Will cause FIFO interrupt when four receive buffers remain

bit 4-0

EWIN4:EWIN0: Enhanced Window Address bits

These bits map the group of 16 banked CAN SFRs into access bank addresses 0F60-0F6Dh.

Exact group of registers to map is determined by binary value of these bits.

Mode 0:

Unimplemented: Read as ‘0’

Mode 1, 2:

00000

= Acceptance Filters 0, 1, 2 and BRGCON2, 3

00001

= Acceptance Filters 3, 4, 5 and BRGCON1, CIOCON

00010

= Acceptance Filter Masks, Error and Interrupt Control

00011

= Transmit Buffer 0

00100

= Transmit Buffer 1

00101

= Transmit Buffer 2

00110

= Acceptance Filters 6, 7, 8

00111

= Acceptance Filters 9, 10, 11

01000

= Acceptance Filters 12, 13, 14

01001

= Acceptance Filters 15

01010

-01110 = Reserved

01111

= RXINT0, RXINT1

10000

= Receive Buffer 0

10001

= Receive Buffer 1

10010

= TX/RX Buffer 0

10011

= TX/RX Buffer 1

10100

= TX/RX Buffer 2

10101

= TX/RX Buffer 3

10110

= TX/RX Buffer 4

10111

= TX/RX Buffer 5

11000

-11111 = Reserved

Note 1: These bits can only be changed in Configuration mode. See Register 23-1 to

change to Configuration mode.

2: This bit is used in Mode 2 only.

3: FIFO length of 4 or less will cause this bit to be set.

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

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