EN25Q64-104FIP datasheet(14/60 Pages) EON

14 / 60 page

This Data Sheet may be revised by subsequent versions

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or modifications due to changes in technical specifications.

EN25Q64

Rev. J, Issue Date: 2011/07/07

Table 3. Protected Area Sizes Sector Organization

Status Register Content

Memory Content

BP3

Bit

BP2

Bit

BP1

Bit

BP0

Bit

Protect Areas

Addresses

Density(KB)

Portion

None

Block 0 to 126

000000h-7EFFFFh

8128KB

Lower 127/128

Block 0 to 125

000000h-7DFFFFh

8064KB

Lower 126/128

Block 0 to 123

000000h-7BFFFFh

7936KB

Lower 124/128

Block 0 to 119

000000h-77FFFFh

7680KB

Lower 120/128

Block 0 to 111

000000h-6FFFFFh

7168KB

Lower 112/128

Block 0 to 95

000000h-5FFFFFh

6144KB

Lower 96/128

All

000000h-7FFFFFh

8192KB

All

None

Block 127 to 1

7FFFFFh-010000h

8128KB

Upper 127/128

Block 127 to 2

7FFFFFh-020000h

8064KB

Upper 126/128

Block 127 to 4

7FFFFFh-040000h

7936KB

Upper 124/128

Block 127 to 8

7FFFFFh-080000h

7680KB

Upper 120/128

Block 127 to 16

7FFFFFh-100000h

7168KB

Upper 112/128

Block 127 to 32

7FFFFFh-200000h

6144KB

Upper 96/128

All

7FFFFFh-000000h

8192KB

All

INSTRUCTIONS

All instructions, addresses and data are shifted in and out of the device, most significant bit first. Serial

Data Input (DI) is sampled on the first rising edge of Serial Clock (CLK) after Chip Select (CS#) is

driven Low. Then, the one-byte instruction code must be shifted in to the device, most significant bit first,

on Serial Data Input (DI), each bit being latched on the rising edges of Serial Clock (CLK).

The instruction set is listed in Table 4. Every instruction sequence starts with a one-byte instruction

code. Depending on the instruction, this might be followed by address bytes, or by data bytes, or by

both or none. Chip Select (CS#) must be driven High after the last bit of the instruction sequence has

been shifted in. In the case of a Read Data Bytes (READ), Read Data Bytes at Higher Speed

(Fast_Read), Dual Output Fast Read (3Bh), Dual I/O Fast Read (BBh), Quad Input/Output

FAST_READ (EBh), Read Status Register (RDSR) or Release from Deep Power-down, and Read

Device ID (RDI) instruction, the shifted-in instruction sequence is followed by a data-out sequence.

Chip Select (CS#) can be driven High after any bit of the data-out sequence is being shifted out.

In the case of a Page Program (PP), Sector Erase (SE), Block Erase (BE), Chip Erase (CE), Write

Status Register (WRSR), Write Enable (WREN), Write Disable (WRDI) or Deep Power-down (DP)

instruction, Chip Select (CS#) must be driven High exactly at a byte boundary, otherwise the instruction

is rejected, and is not executed. That is, Chip Select (CS#) must driven High when the number of clock

pulses after Chip Select (CS#) being driven Low is an exact multiple of eight. For Page Program, if at

any time the input byte is not a full byte, nothing will happen and WEL will not be reset.

In the case of multi-byte commands of Page Program (PP), and Release from Deep Power Down

(RES ) minimum number of bytes specified has to be given, without which, the command will be

ignored.

In the case of Page Program, if the number of byte after the command is less than 4 (at least 1

data byte), it will be ignored too. In the case of SE and BE, exact 24-bit address is a must, any

less or more will cause the command to be ignored.

All attempts to access the memory array during a Write Status Register cycle, Program cycle or Erase

cycle are ignored, and the internal Write Status Register cycle, Program cycle or Erase cycle continues

unaffected.

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